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ATtiny48 Datasheet(PDF) 136 Page - ATMEL Corporation

Part # ATtiny48
Description  8-bit Microcontroller with 4/8K Bytes In-System Programmable Flash
PDF  266 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATtiny48 Datasheet(HTML) 136 Page - ATMEL Corporation

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136
8008C–AVR–03/09
ATtiny48/88
The following sections describe each of these modes. Possible status codes are described
along with figures detailing data transmission in each of the modes. These figures contain the
following abbreviations:
S: START condition
Rs: REPEATED START condition
R: Read bit (high level at SDA)
W: Write bit (low level at SDA)
A: Acknowledge bit (low level at SDA)
A: Not acknowledge bit (high level at SDA)
Data: 8-bit data byte
P: STOP condition
SLA: Slave Address
In Figure 15-12 to Figure 15-18, circles are used to indicate that the TWINT Flag is set. The
numbers in the circles show the status code held in TWSR, with the prescaler bits masked to
zero. At these points, actions must be taken by the application to continue or complete the TWI
transfer. The TWI transfer is suspended until the TWINT Flag is cleared by software.
When the TWINT Flag is set, the status code in TWSR is used to determine the appropriate soft-
ware action. For each status code, the required software action and details of the following serial
transfer are given in Table 15-2 to Table 15-5. Note that the prescaler bits are masked to zero in
these tables.
15.7.1
Master Transmitter Mode
In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver
(see Figure 15-11). In order to enter a Master mode, a START condition must be transmitted.
The format of the following address packet determines whether Master Transmitter or Master
Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is trans-
mitted, MR mode is entered. All the status codes mentioned in this section assume that the
prescaler bits are zero or are masked to zero.
Figure 15-11. Data Transfer in Master Transmitter Mode
Device 1
MASTER
TRANSMITTER
Device 2
SLAVE
RECEIVER
Device 3
Device n
SDA
SCL
........
R1
R2
V
CC



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