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ATtiny48 Datasheet(PDF) 140 Page - ATMEL Corporation |
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ATtiny48 Datasheet(HTML) 140 Page - ATMEL Corporation |
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140 / 266 page ![]() 140 8008C–AVR–03/09 ATtiny48/88 Figure 15-13. Data Transfer in Master Receiver Mode A START condition is sent by writing the following value to TWCR: TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag. The TWI will then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT Flag is set by hard- ware, and the status code in TWSR will be 0x08 (See Table 15-2). In order to enter MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR: When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes is detailed in Table 15-3. Received data can be read from the TWDR Register when the TWINT Flag is set high by hardware. This scheme is repeated until the last byte has been received. After the last byte has been received, the MR should inform the ST by sending a NACK after the last received data byte. The transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR: A REPEATED START condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 1 X1 0 X1 0 X TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 1 X0 0 X1 0 X TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 1 X0 1 X1 0 X TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 1 X1 0 X1 0 X Device 1 MASTER RECEIVER Device 2 SLAVE TRANSMITTER Device 3 Device n SDA SCL ........ R1 R2 V CC |
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