ATtiny48 datasheet(154/266 Pages) ATMEL

154 / 266 page

154

8008C–AVR–03/09

ATtiny48/88

• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit

If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.

15.9.6

TWAMR – TWI (Slave) Address Mask Register–

• Bits 7..1 – TWAM: TWI Address Mask

The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can

mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask

bit is set to one then the address match logic ignores the compare between the incoming

address bit and the corresponding bit in TWAR. Figure 15-22 shown the address match logic in

detail.

Figure 15-22. TWI Address Match Logic, Block Diagram

• Bit 0 – Res: Reserved Bit

These bits are reserved and will always read zero.

15.9.7

TWHSR – TWI High Speed Register

• Bits 7..1 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bit 0 – TWHS: TWI High Speed Enable

TWI High Speed mode is enabled by writing this bit to one. In this mode the undivided system

clock is selected as TWI clock. See Figure 6-1 on page 25.

The TWI High Speed mode requires that the high-speed clock, clk

TWIHS, is exactly two times

higher than the I/O clock frequency, clk

I/O. This means the user must make sure the I/O clock

frequency clk

I/O is scaled down by a factor of 2. For example, if the internal 8 MHz oscillator has

been selected as source clock, the user must set the prescaler to scale the system clock (and,

hence, the I/O clock) down to 4 MHz. For more information about clock systems, see “Clock

Systems and their Distribution” on page 25.

Bit

654

TWAM[6:0]

–

TWAMR

Read/Write

R/W

Initial Value

Address

Match

Address Bit Comparator 0

Address Bit Comparator 6..1

TWAR0

TWAMR0

Address

Bit 0

Bit

654

–

–––

––

–

TWHS

TWHSR

Read/Write

R/W

Initial Value

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