ATtiny48 datasheet(165/266 Pages) ATMEL

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8008C–AVR–03/09

ATtiny48/88

selection. Since the next conversion has already started automatically, the next result will reflect

the previous channel selection. Subsequent conversions will reflect the new channel selection.

17.6.2

ADC Voltage Reference

The ADC reference voltage (V

REF) indicates the conversion range for the ADC. Single ended

channels that exceed V

REF will result in codes close to 0x3FF. VREF can be selected as either

CC, or internal 1.1V reference. The internal 1.1V reference is generated from the internal

bandgap reference (V

BG) through an internal amplifier.

The first ADC conversion result after switching reference voltage source may be inaccurate, and

the user is advised to discard this result.

17.7

ADC Noise Canceler

The ADC features a noise canceler that enables conversion during sleep mode. This reduces

noise induced from the CPU core and other I/O peripherals. The noise canceler can be used

with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure

should be used:

• Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must

be selected and the ADC conversion complete interrupt must be enabled.

• Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the

CPU has been halted.

• If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake

up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt

wakes up the CPU before the ADC conversion is complete, that interrupt will be executed,

and an ADC Conversion Complete interrupt request will be generated when the ADC

conversion completes. The CPU will remain in active mode until a new sleep command is

executed.

Note that the ADC will not automatically be turned off when entering other sleep modes than Idle

mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-

ing such sleep modes to avoid excessive power consumption.

17.8

Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 17-8 An analog

source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regard-

less of whether that channel is selected as input for the ADC. When the channel is selected, the

source must drive the S/H capacitor through the series resistance (combined resistance in the

input path).

The ADC is optimized for analog signals with an output impedance of approximately 10k

Ω or

less. If such a source is used, the sampling time will be negligible. If a source with higher imped-

ance is used, the sampling time will depend on how long time the source needs to charge the

S/H capacitor, which can vary widely. With slowly varying signals the user is recommended to

use sources with low impedance, only, since this minimizes the required charge transfer to the

S/H capacitor.

In order to avoid distortion from unpredictable signal convolution, signal components higher than

the Nyquist frequency (f

ADC/2) should not be present. The user is advised to remove high fre-

quency components with a low-pass filter before applying the signals as inputs to the ADC.

ATtiny48 Datasheet(PDF) 165 Page - ATMEL Corporation

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