ATtiny48 datasheet(162/266 Pages) ATMEL

162 / 266 page

162

8008C–AVR–03/09

ATtiny48/88

The ADC module contains a prescaler, as illustrated in Figure 17-3 on page 161, which gener-

ates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The

prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment

the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as

long as the ADEN bit is set, and is continuously reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion

starts at the following rising edge of the ADC clock cycle.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched

on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry,

as shown in Figure 17-4 below.

Figure 17-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-

sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is

complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion

mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new

conversion will be initiated on the first rising ADC clock edge.

Figure 17-5. ADC Timing Diagram, Single Conversion

Sign and MSB of Result

LSB of Result

ADC Clock

ADSC

Sample & Hold

ADIF

ADCH

ADCL

Cycle Number

ADEN

212

First Conversion

Conversion

MUX and REFS

Update

MUX and REFS

Update

Conversion

Complete

Sign and MSB of Result

LSB of Result

ADC Clock

ADSC

ADIF

ADCH

ADCL

Cycle Number

One Conversion

Next Conversion

Sample & Hold

MUX and REFS

Update

Conversion

Complete

MUX and REFS

Update

ATtiny48 Datasheet(PDF) 162 Page - ATMEL Corporation

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