ATtiny48 datasheet(180/266 Pages) ATMEL

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180

8008C–AVR–03/09

ATtiny48/88

19.1.3

Preventing Flash Corruption

During periods of low V

CC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating

voltage matches the detection level. If not, an external low V

CC reset protection circuit

can be used. If a reset occurs while a write operation is in progress, the write operation

will be completed provided that the power supply voltage is sufficient.

Keep the AVR core in Power-down sleep mode during periods of low V

CC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

19.1.4

Programming Time for Flash when Using SPM

The calibrated oscillator is used to time Flash accesses. Table 19-1 shows the typical program-

ming time for Flash accesses from the CPU.

19.1.5

Simple Assembly Code Example for a Boot Loader

Note that the RWWSB bit will always be read as zero in ATtiny48/88. Nevertheless, to ensure

compatibility with devices supporting Read-While-Write it is recommended to check this bit as

shown in the code example.

;-the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y pointer

; the first data location in Flash is pointed to by the Z-pointer

;-error handling is not included

;-the routine must be placed inside the Boot space

; (at least the Do_spm sub routine). Only code inside NRWW section can

; be read during Self-Programming (Page Erase and Page Write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

; loophi (r25), spmcrval (r20)

; storing and restoring of registers is not included in the routine

; register usage can be optimized at the expense of code size

;-It is assumed that either the interrupt table is moved to the Boot

; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2

;PAGESIZEB is page size in BYTES, not words

.org SMALLBOOTSTART

Table 19-1.

SPM Programming Time

Symbol

Min Programming Time

Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM)

3.7 ms

4.5 ms

ATtiny48 Datasheet(PDF) 180 Page - ATMEL Corporation

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