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ATtiny48 Datasheet(PDF) 182 Page - ATMEL Corporation |
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ATtiny48 Datasheet(HTML) 182 Page - ATMEL Corporation |
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182 / 266 page  182 8008C–AVR–03/09 ATtiny48/88 sbrc temp1, SELFPRGEN rjmp Wait_spm ; input: spmcrval determines SPM action ; disable interrupts if enabled, store status in temp2, SREG cli ; check that no EEPROM write access is present Wait_ee: sbic EECR, EEPE rjmp Wait_ee ; SPM timed sequence out SPMCSR, spmcrval spm ; restore SREG (to enable interrupts if originally enabled) out SREG, temp2 ret 19.2 Register Description 19.2.1 SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to con- trol the Program memory operations. • Bit 7 – Res: Reserved Bit These bits are reserved and will always read zero. • Bit 6 – RWWSB: Read-While-Write Section Busy This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero in ATtiny48/88. • Bit 5 – Res: Reserved Bit These bits are reserved and will always read zero. • Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost. • Bit 3 – RFLB: Read Fuse and Lock Bits An LPM instruction within three cycles after RFLB and SELFPRGEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 179 for details. • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The Bit 7 6 5 4 3 2 1 0 - RWWSB – CTPB RFLB PGWRT PGERS SELFPRGEN SPMCSR Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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