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MB95430 Datasheet(PDF) 40 Page - fujitsu semiconductor

Part # MB95430
Description  8-bit Microcontrollers
PDF  56 Pages
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Manufacturer  FUJITSU [fujitsu semiconductor]
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Logo FUJITSU - fujitsu semiconductor

MB95430 Datasheet(HTML) 40 Page - fujitsu semiconductor

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MB95430H Series
40
DS07–12xxx–1E
(VCC = 5.0 V
±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
(Continued)
Parameter
Sym-
bol
Pin
name
Condition
Value*2
Unit
Remarks
Min
Max
SCL clock “L”
width
tLOW
SCL
R = 1.7 k
Ω,
C = 50 pF*1
(2
+ nm/2)tMCLK − 20
—
ns
Master mode
SCL clock “H”
width
tHIGH SCL
(nm/2)tMCLK
− 20
(nm/2)tMCLK
+ 20
ns
Master mode
START
condition hold
time
tHD;STA
SCL,
SDA
(
−1 + nm/2)tMCLK − 20
(
−1 + nm)tMCLK + 20
ns
Master mode
Maximum value
is applied when
m, n = 1, 8.
Otherwise, the
minimum value
is applied.
STOP
condition
setup time
tSU;STO
SCL,
SDA
(1
+ nm/2)tMCLK − 20
(1
+ nm/2)tMCLK + 20
ns
Master mode
START
condition
setup time
tSU;STA
SCL,
SDA
(1
+ nm/2)tMCLK − 20
(1
+ nm/2)tMCLK + 20
ns
Master mode
Bus free time
between
STOP
condition and
START
condition
tBUF
SCL,
SDA
(2 nm
+ 4)tMCLK − 20
—ns
Data hold
time
tHD;DAT
SCL,
SDA
3 tMCLK
− 20
—
ns
Master mode
Data setup
time
tSU;DAT
SCL,
SDA
(
−2 + nm/2)tMCLK − 20 (−1 + nm/2)tMCLK + 20
ns
Master mode
When assuming
that “L” of SCL is
not extended,
the minimum
value is applied
to first bit of
continuous data.
Otherwise, the
maximum value
is applied.
Setup time
between
clearing inter-
rupt and SCL
rising
tSU;INT SCL
(nm/2)tMCLK
− 20
(1
+ nm/2)tMCLK + 20
ns
Minimum value
is applied to
interrupt at 9th
SCL
↓. Maximum
value is applied
to the interrupt at
the 8th SCL
↓.



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