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MB95430 Datasheet(PDF) 33 Page - fujitsu semiconductor |
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MB95430 Datasheet(HTML) 33 Page - fujitsu semiconductor |
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33 / 56 page  MB95430H Series DS07–12xxx–1E 33 FCH (main oscillation) FCRH (Main CR clock) FCL (sub-oscillation) FCRL (Sub-CR clock) SCLK (source clock) MCLK (machine clock) Machine clock divide ratio select bits (SYCC:DIV1, DIV0) Clock mode select bits (SYCC2: RCS1, RCS0) Division circuit × × × × 1 1/4 1/8 1/16 Divided by 2 Divided by 2 Divided by 2 • Schematic diagram of the clock generation block A/D converter operation range 5.5 5.0 4.0 3.5 3.0 2.4 16 kHz 3 MHz 10 MHz 16.25 MHz Source clock frequency (FSP/FSPL) A/D converter operation range 5.5 5.0 4.0 3.5 3.0 2.9 16 kHz 3 MHz 12.5 MHz 16.25 MHz Source clock frequency (FSP) • Operating voltage - Operating frequency (When TA = −40°C to +85°C) MB95430H (without the on-chip debug function) • Operating voltage - Operating frequency (When TA = −40°C to +85°C) MB95430H (with the on-chip debug function) |
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