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MB95430 Datasheet(PDF) 32 Page - fujitsu semiconductor |
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MB95430 Datasheet(HTML) 32 Page - fujitsu semiconductor |
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32 / 56 page  MB95430H Series 32 DS07–12xxx–1E (2) Source Clock/Machine Clock (VCC = 5.0 V ±10%, VSS = 0.0 V, TA = −40°C to +85°C) *1: This is the clock before it is divided according to the division ratio set by the machine clock divide ratio select bits (SYCC:DIV1 and DIV0). This source clock is divided to become a machine clock according to the divide ratio set by the machine clock divide ratio select bits (SYCC:DIV1 and DIV0). In addition, a source clock can be selected from the following. • Main clock divided by 2 • Main CR clock • Subclock divided by 2 • Sub-CR clock divided by 2 *2: This is the operating clock of the microcontroller. A machine clock can be selected from the following. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 Parameter Symbol Pin name Value Unit Remarks Min Typ Max Source clock cycle time*1 tSCLK — 61.5 — 2000 ns When the main external clock is used Min: FCH = 32.5 MHz, divided by 2 Max: FCH = 1 MHz, divided by 2 80 — 1000 ns When the main CR clock is used Min: FCRH = 12.5 MHz Max: FCRH = 1 MHz —61 — µs When the sub-oscillation clock is used FCL = 32.768 kHz, divided by 2 —20 — µs When the sub-CR clock is used FCRL = 100 kHz, divided by 2 Source clock frequency FSP — 0.5 — 16.25 MHz When the main oscillation clock is used 1 — 12.5 MHz When the main CR clock is used FSPL — 16.384 — kHz When the sub-oscillation clock is used — 50 — kHz When the sub-CR clock is used FCRL = 100 kHz, divided by 2 Machine clock cycle time*2 (minimum instruction execution time) tMCLK — 61.5 — 32000 ns When the main oscillation clock is used Min: FSP = 16.25 MHz, no division Max: FSP = 0.5 MHz, divided by 16 80 — 16000 ns When the main CR clock is used Min: FSP = 12.5 MHz Max: FSP = 1 MHz, divided by 16 61 — 976.5 µs When the sub-oscillation clock is used Min: FSPL = 16.384 kHz, no division Max: FSPL = 16.384 kHz, divided by 16 20 — 320 µs When the sub-CR clock is used Min: FSPL = 50 kHz, no division Max: FSPL = 50 kHz, divided by 16 Machine clock frequency FMP — 0.031 — 16.25 MHz When the main oscillation clock is used 0.0625 — 12.5 MHz When the main CR clock is used FMPL 1.024 — 16.384 kHz When the sub-oscillation clock is used 3.125 — 50 kHz When the sub-CR clock is used FCRL = 100 kHz |
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