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AM3892 Datasheet(PDF) 115 Page - Texas Instruments

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Part # AM3892
Description  AM389x Sitara ARM Microprocessors (MPUs)
PDF  299 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3892 Datasheet(HTML) 115 Page - Texas Instruments

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USB 2.0
0/1
Cortex™-
A8
SGX530
(A)
DMM
SATA
EMAC1
PCIe
Gen2
McASP0
L4 Periph
High Speed
Media
Ctrl
L4 Periph
Standard
HDMI 1.3
Tx
McASP2
Media
Ctrl
EMAC0
EDMA
4 Channels
USB 2.0
Target Ports
Initiator Ports
Debug
PCIe
Gen2
GPMC
SGX530
(A)
McBSP
OCMC
RAM1
McASP1
OCMC
RAM0
Debug
DAP
EDMA
Config
HDVPSS
DDR
AM3894
AM3892
www.ti.com
SPRS681A – OCTOBER 2010 – REVISED MARCH 2011
5
System Interconnect
The L3 interconnect allows the sharing of resources, such as peripherals and external or on-chip
memories, between all the initiators of the platform. The L4 interconnects control access to the
peripherals.
Transfers between initiators and targets across the platform are physically conditioned by the chip
interconnect.
5.1
L3 Interconnect
The L3 topology is driven by performance requirements, bus types, and clocking structure. Figure 5-1
shows the interconnect of the device and the main modules and subsystems in the platform. Arrows
indicate the master/slave relationship, not data flow. Master/slave connectivity is shown in Table 5-1.
A.
SGX530 is available only on the AM3894 device.
Figure 5-1. Interconnect Overview
Copyright © 2010–2011, Texas Instruments Incorporated
System Interconnect
115
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