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AM3892 Datasheet(PDF) 117 Page - Texas Instruments

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Part # AM3892
Description  AM389x Sitara ARM Microprocessors (MPUs)
PDF  299 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3892 Datasheet(HTML) 117 Page - Texas Instruments

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L4 High Speed
EMAC
EMAC
SATA
0
1
Spinlock
PRCM
Control
ELM
HDMIphy
OCPWP
McASP
McASP
McASP
Mailbox
0
1
2
L4 Standard
I
I
SPI
UART
UART
Timer
Timer
Timer
Timer
Timer
Timer
Timer
GPIO
GPIO
SD
WDT
RTC
S
S
DDR
DDR
2C0
2C1
0
1
1
2
3
4
5
6
7
0
1
/SDIO
martReflex0
martReflex1
_CFG0
_CFG1
250-MHz CLK domain
125-MHz CLK domain
L3 Interconnect
AM3894
AM3892
www.ti.com
SPRS681A – OCTOBER 2010 – REVISED MARCH 2011
5.2
L4 Interconnect
The L4 interconnect is a non-blocking peripheral interconnect that provides low-latency access to a large
number of low-bandwidth, physically-dispersed target cores. The L4 can handle incoming traffic from up to
four initiators and can distribute those communication requests to and collect related responses from up to
63 targets.
The device provides three interfaces with L3 interconnect for high-speed peripheral and standard
peripheral. Figure 5-2 and Table 5-2 show the L4 bus architecture and memory-mapped peripherals.
A.
SGX530 is available only on the AM3894 device.
Figure 5-2. L4 Architecture
Copyright © 2010–2011, Texas Instruments Incorporated
System Interconnect
117
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Product Folder Link(s): AM3894 AM3892



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