AM3892 datasheet(120/299 Pages) TI

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AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

www.ti.com

6.2

Recommended Operating Conditions

(1)

PARAMETER

MIN

NOM

MAX

UNIT

Supply voltage, Variable Core, Adaptive Voltage

CVDD

0.8

1.05

Scaling (CVDD)(2)

Supply voltage, Constant Core (CVDDC,

CVDDC

VDDT_SATA, VDDT_PCIE, VDDA_HDMI,

0.95

1.05

VDDA_HD_1P0, VDDA_SD_1P0)

Supply voltage, I/O, 3.3 V (DVDD_3P3,

VDD_USB0_3P3, VDD_USB1_3P3)

3.13

3.3

3.47

(except I2C pins)

Supply voltage, I/O, I2C (DVDD_3P3)

3.13

3.3

3.47

Supply voltage, I/O, 1.8 V (DVDD1P8,

DEVOSC_DVDD18, VDD_USB0_1P8,

DVDD

VDD_USB1_1P8, VDDA_REF_1P8,

1.71

1.8

1.89

VDDA_HD_1P8, VDDA_SD_1P8, DVDD_DDR0,

DVDD_DDR1)(3)

Supply voltage, I/O, 1.5 V (VDDA_PLL,

VDDR_SATA, VDDR_PCIE, DVDD_DDR0,

1.43

1.5

1.58

DVDD_DDR1)(3)

Supply voltage, I/O, 0.9 V (VDD_USB_0P9)

0.85

0.9

0.95

Supply ground (VSS, VSSA_PLL, VSSA_HD,

VSS

VSSA_SD, VSSA_REF_1P8, DEVOSC_VSS)(4)

DDR_VREF

DDR2/3 reference voltage(5)

0.48DVDD_DDRx

0.5DVDD_DDRx

0.52DVDD_DDRx

High-level input voltage, 3.3 V (except I2C pins)

VIH

High-level input voltage, I2C

0.7DVDD_3P3

High-level input voltage, 1.8 V

0.65DVDD1P8

Low-level input voltage, 3.3 V (except I2C pins)

0.8

VIL

Low-level input voltage, I2C

0.3DVDD_3P3

Low-level input voltage, 1.8 V

0.35DVDD1P8

4-mA I/O buffers

-4

6-mA I/O buffers

-6

IOH

High-level output current

DDR[0], DDR[1]

buffers @ 50-

-8

impedance setting

4-mA I/O buffers

6-mA I/O buffers

IOL

Low-level output current

DDR[0], DDR[1]

buffers @ 50-

impedance setting

Differential input voltage (SERDES_CLKN/P),

0.25

VID

2.0

[AC coupled]

Transition time, 10%-90%, All Inputs (unless

Lesser of 0.25P or

otherwise specified in the electrical data sections)

10 (6)

(1)

Data in this table is based on device operation at 1.0 GHz for the ARM Cortex-A8.

(2)

This device supports, and requires the use of, SmartReflex technology with Adaptive Voltage Scaling based on die temperature and

performance. The SmartReflex codes output from the device correspond to up to 32 linear voltage steps within the specified voltage

range, with the option to use fewer steps if desired, with a minimum of eight steps. TI requires that users design-in a supply that can

handle multiple voltage steps within this range with ± 5% tolerances. Not incorporating a flexible supply may limit the system's ability to

use the power saving capabilities of the SmartReflex technology.

(3)

For supply voltage pins, DVDD_DDRx:

•

1.5 V is used for DDR3 SDRAM.

•

1.8 V is used for DDR2 SDRAM.

(4)

Oscillator ground (DEVOSC_VSS) must be kept separate from other grounds and connected directly to the crystal load capacitor

ground.

(5)

DDR_VREF is expected to equal 0.5DVDD_DDRx of the transmitting device and to track variations in the DVDD_DDRx.

(6)

P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input

signals.

120

Device Operating Conditions

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