AM3892 datasheet(124/299 Pages) TI

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AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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7.1.4

SmartReflex™

The device contains SmartReflex modules that are required to minimize power consumption on the

voltage domains using external variable-voltage power supplies. Based on the device process,

temperature, and desired performance, the SmartReflex modules advise the host processor to raise or

lower the supply voltage to each domain for minimal power consumption. The communication link between

the host processor and the external regulators is a system-level decision and can be accomplished using

GPIOs or I2C.

The major technique employed by SmartReflex in the device is adaptive voltage scaling (AVS). Based on

the silicon process and temperature, the SmartReflex modules guide software in adjusting the core 1-V

supply voltage within the desired range. This technique is called adaptive voltage scaling (AVS). AVS

occurs continuously and in real time, helping to minimize power consumption in response to changing

operating conditions.

NOTE

Implementation of SmartReflex AVS is required for proper device operation.

7.1.5

Memory Power Management

The device memories offer three different modes to save power when memories are not being used;

Table 7-1 provides the details.

Table 7-1. Memory Power Management Modes

MODE

POWER SAVING

WAKE-UP LATENCY

MEMORY CONTENTS

Light Sleep (LS)

~60%

Low

Preserved

Deep Sleep (DS)

~75%

Medium

Preserved

Shut Down (SD)

~95%

High

Lost

The device provides a feature that allows the software to put the chip-level memories (OCMC RAMs) in

any of the three (LS, DS, and SD) modes. There are control registers in the control module to control the

power-down state of OCMC RAM0 and OCMC RAM1. There are also status registers that can be used

during power-up to check if memories are powered-up. For detailed instructions on entering and exiting

from light sleep and deep sleep modes, see the AM38x Sitara ARM Microprocessors (MPUs) Technical

Reference Manual (literature number SPRUGX7).

Memories inside switchable domains go to the shut down (SD) state whenever the power domain goes to

the OFF state. Memories come back to functional state along with the domain power-up.

In order to reduce SRAM leakage, many SRAM blocks can be switched from active mode to shut-down

mode. When SRAM is put in shut-down mode, the voltage supplied to it is automatically removed and all

data in that SRAM is lost.

All SRAM located in a switchable power domain (all domains except always-on) automatically enters

shut-down mode whenever its assigned associated power domain goes to the OFF state. The SRAM

returns to the active state when the corresponding power domain returns to the ON state.

For detailed instructions on powering up/down the various device SRAM, see the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

7.1.6

I/O Power-Down Modes

The DDR3 I/Os are put into power-down mode automatically when the default power domain is turned

OFF.

The HDMI PHY controller is in the always-on power domain, so software must configure the PHY into

power-down mode.

124

Power, Reset, Clocking, and Interrupts

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