AM3892 datasheet(128/299 Pages) TI

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AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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7.2.9

Local Reset

The local reset for various modules within the device is controlled by programming the PRCM and/or the

module's internal registers. Only the associated module is reset when a local reset is asserted, leaving the

rest of the device unaffected.

For details on local reset, see the PRCM chapter of the AM38x Sitara ARM Microprocessors (MPUs)

Technical Reference Manual (literature number SPRUGX7) and individual subsystem and peripheral

user's guides.

7.2.10 Reset Priority

If any of the above reset sources occur simultaneously, the device only processes the highest-priority

reset request. The reset request priorities, from high to low, are as follows:

1. Power-on reset (POR)

2. Test reset (TRST)

3. External warm reset (RESET)

4. Emulation warm resets

5. Watchdog reset

6. Software global cold/warm resets.

7.2.11 Reset Status Register

The Reset Status Register (PRM_RSTST) contains information about the last reset that occurred in the

system. For more information on this register, see the PRCM chapter of the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

7.2.12 PCIe Reset Isolation

The device supports reset isolation for the PCI Express (PCIe) module. This means that the PCI Express

subsystem can be reset without resetting the rest of the device.

When the device is a PCI Express Root Complex (RC), the PCIe subsystem can be reset by software

through the PRCM. Software should ensure that there are no ongoing PCIe transactions before asserting

this reset by first taking the PCIe subsystem into the IDLE state by programming the register

CM_DEFAULT_PCI_CLKCTRL inside the PRCM. After bringing the PCIe subsystem out of reset, bus

enumeration should be performed again and should treat all endpoints (EP) as if they had just been

connected.

When the device is a PCI Express Endpoint (EP), the PCIe subsystem generates an interrupt when an

in-band reset is received. Software should process this interrupt by putting the PCIe subsystem in the

IDLE state and then asserting the PCIe local reset through the PRCM.

All device-level resets mentioned in the previous sections, except Test Reset, also reset the PCIe

subsystem. Therefore, the device should issue a Hot Reset to all downstream devices and re-enumerate

the bus upon coming out of reset.

7.2.13 RSTOUT

The RSTOUT pin on the device reflects device reset status. This output is always asserted when any of

the following resets occur:

•

Power-on reset (POR)

•

External warm reset

•

Emulation warm reset (RESET)

•

Software global cold/warm reset

•

Watchdog timer reset.

128

Power, Reset, Clocking, and Interrupts

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