AM3892 datasheet(129/299 Pages) TI

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AM3894

AM3892

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SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

The RSTOUT pin remains asserted until PRCM releases the host ARM Cortex-A8 processor for reset.

7.2.14 Effect of Reset on Emulation and Trace

The device emulation and trace is only reset by the following sources:

•

Power-on reset (POR)

•

Software global cold reset

•

Test reset (TRST).

Other than these three, none of the other resets affect emulation and trace functionality.

7.2.15 Reset During Power Domain Switching

Each power domain has a dedicated warm reset and cold reset. Warm reset for a power domain is

asserted under either of the following two conditions:

1. A power-on reset, external warm reset, emulation warm reset, or software global cold/warm reset

occurs.

2. When that power domain switches from the ON state to the OFF state.

Cold reset for a power domain is asserted under either of the following two conditions:

1. A power-on reset or software global cold reset occurs.

2. When that power domain switches from the OFF state to the ON state.

7.2.16 Pin Behaviors at Reset

When any reset (other than test reset) described in Section 7.2.1 is asserted, all device pins are put into a

Hi-Z state except for:

•

Emulation pins. These pins are only put into a Hi-Z state when POR or global software cold reset is

asserted.

•

RSTOUT pin.

In addition, the PINCNTL registers, which control pin multiplexing, slew control, enabling the

pullup/pulldown, and enabling the receiver, are reset to their default state. For a description of the

RESET_ISO register, see the AM38x Sitara ARM Microprocessors (MPUs) Technical Reference Manual

(literature number SPRUGX7).

Internal pullup/pulldown (IPU/IPD) resistors are enabled during and immediately after reset as described in

the OTHER column in the tables in Section 3.2, Terminal Functions.

7.2.17 Reset Electrical Data/Timing

NOTE

If a configuration pin must be routed out from the device, the internal pullup/pulldown

(IPU/IPD) resistor should not be relied upon; TI recommends the use of an external

pullup/pulldown resistor.

Table 7-3. Timing Requirements for Reset

(see Figure 7-2 and Figure 7-3)

NO.

MIN

MAX

UNIT

tw(RESET)

Pulse duration, POR low or RESET low

12C(1)

tsu(CONFIG)

Setup time, boot and configuration pins valid before POR high or RESET

12C(1)

high(2)

(1)

C = 1/DEV_MXI clock frequency, in ns. The device clock source must be stable and at a valid frequency prior to meeting the tw(RESET)

requirement.

(2)

For the list of boot and configuration pins, see , Boot Terminal Functions.

Power, Reset, Clocking, and Interrupts

129

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