AM3892 datasheet(130/299 Pages) TI

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RESET STATE

DEV_CLKIN

POR

RESET

BTMODE[4:0]

Other I/O Pins

(A)

Power

Supplies

Ramping

Power Supplies Stable

Clock Source Stable

Config

Hi-Z

AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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Table 7-3. Timing Requirements for Reset (continued)

(see Figure 7-2 and Figure 7-3)

NO.

MIN

MAX

UNIT

th(CONFIG)

Hold time, boot and configuration pins valid after POR high or RESET

high(2)

Table 7-4. Switching Characteristics Over Recommended Operating Conditions During Reset

(see Figure 7-2)

NO.

PARAMETER

MIN

MAX

UNIT

tw(RSTL)

Pulse width, RESET low

10C(1)

td(RSTL_IORST)

Delay time, RESET falling to all IO entering their reset state

td(RSTL_IOFUNC)

Delay time, RESET rising to IO exiting their reset state

(1)

C = 1/DEV_CLKIN clock frequency, in ns.

For more detailed information on the reset state of each pin, see Section 7.2.16, Pin Behaviors at Reset. For the

IPU/IPD settings during reset, see Section 3.2, Terminal Functions.

Figure 7-2. Power-Up Timing

130

Power, Reset, Clocking, and Interrupts

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