AM3892 datasheet(134/299 Pages) TI

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DEV_CLKIN

AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

www.ti.com

Table 7-6. DEV_CLKIN Clock Source Requirements(1)(2)(3)

(see Figure 7-6)

NO.

MIN

NOM

MAX

UNIT

tc(DCK)

Cycle time, DEV_CLKIN

37.037

tw(DCKH)

Pulse duration, DEV_CLKIN high

0.45C

0.55C

tw(DCKL)

Pulse duration, DEV_CLKIN low

0.45C

0.55C

tt(DCK)

Transition time, DEV_CLKIN

tJ(DCK)

Period jitter, DEV_CLKIN (VDACs not used)

150

Period jitter, DEV_CLKIN (VDACs used)

Frequency stability, DEV_CLKIN

±50

ppm

(1)

The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

(2)

C = DEV_CLKIN cycle time in ns.

(3)

Where SNR is the desired signal-to-noise ratio and BW is the highest DAC signal bandwidth used in the system (SD = 6 MHz,

720p/1080i = 30 MHz, 1080p = 60 MHz).

Figure 7-6. DEV_CLKIN Timing

7.3.2

SERDES_CLKN/P Input Clock

A high-quality, low-jitter differential clock source is required for the PCIe and SATA PHYs. The clock is

required to be AC coupled to the device's SERDES_CLKP and SERDES_CLKN pins according to the

specifications in Table 7-10. Both the clock source and the coupling capacitors should be placed

physically as close as possible to the processor.

When the PCIe interface is used, the SERDES_CLKN/P clock is required to meet the REFCLK AC

specifications outlined in the PCI Express Card Electromechanical Specification (Gen.1 and Gen.2). When

the SATA interface is used, the SERDES_CLKN/P clock is required to meet the specifications in

Table 7-7. When both the PCIe and SATA interfaces are used, both sets of specifications must be met

simultaneously.

Table 7-7. SERDES_CLKN/P Clock Source Requirements for SATA

PARAMETER

MIN

TYP

MAX

UNIT

Clock Frequency

100

MHz

Jitter

Ps pk-pk

Duty Cycle

Rise/Fall Time

700

An HCSL differential clock source is required to meet the REFCLK AC specifications outlined in the PCI

Express Card Electromechanical Specification, Rev. 2.0, at the input to the AC coupling capacitors. In

addition, LVDS clock sources that are compliant to the above specification, but with the exceptions shown

in Table 7-8, are also acceptable.

134

Power, Reset, Clocking, and Interrupts

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