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AM3892 Datasheet(PDF) 137 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 137 Page - Texas Instruments |
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137 / 299 page  AM3894 AM3892 www.ti.com SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 from the main PLL output • H = 10 if M * FREQ is a multiple of 8; otherwise, H = 0 • 800 MHz ≤ PLL_CLKIN * N / P ≤ 1600 MHz • 10 MHz ≤ PLL_CLKIN / P ≤ 60 MHz Table 7-12. PLL Clock Frequencies CLOCK MIN CYCLE MAX FREQUENCY Main PLL Clock1 985 987 Clock2 842 1152 Clock3 1847 532 Clock4 1991 494 DDR PLL Clock 2 18447 54 Clock 3 2443 405 Video PLL Clock 1 1485 660 Clock 2 1485 660 Clock 3 1485 660 Audio PLL Clock 2 6290 158 Clock 3 5041 197 Clock 4 10000 100 Clock 5 10000 100 7.3.4.2 PLL Power Supply Filtering The device PLLs are supplied externally via the VDDA_PLL power-supply pins. External filtering must be added on the PLL supply pins to ensure that the requirements in Table 7-13 are met. Table 7-13. Power Supply Requirements PARAMETER MIN MAX UNIT Dynamic noise at VDDA_PLL pins 50 mV p-p 7.3.4.3 PLL Locking Sequence All of the flying-adder PLLs (except the DDR PLL) come-up in bypass mode at reset. All of the registers (P, N, FREQ, and M) need to be programmed appropriately and then wait approximately 8 µs for PLL_Audio and 5 µs for the other PLLS to be locked. Verification that the PLL is locked can be checked by accessing the lock status bit in the PLL control register for each PLL (bit = 1 when the PLL is locked). Once the PLL is locked, then the FA-PLL can be taken out of bypass mode. Control for bypass mode is through chip-level registers. For more details on the PLL registers and bypass logic, see the PLL chapter of the AM38x Sitara ARM Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7). 7.3.4.4 PLL Registers The PLL control registers reside in the control module and are listed in Table 4-3. Copyright © 2010–2011, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 137 Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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