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AM3892 Datasheet(PDF) 141 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 141 Page - Texas Instruments |
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141 / 299 page  AM3894 AM3892 www.ti.com SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 7.4 Interrupts The device has a large number of interrupts. It also has the ARM Cortex™-A8 master capable of servicing interrupts. Specific details, such as the processing flow, configuration steps, and interrupt controller registers, for each of these masters are found in their respective subsystem documentation. 7.4.1 Interrupt Summary List Table 7-17 lists all the device interrupts by module and indicates the interrupt destination: ARM Cortex™-A8. Table 7-17. Interrupts By Module DESTINATION MODULE INTERRUPT DESCRIPTION Cortex™-A8 INTRQ Serial ATA SATA Module interrupt INTRQ_PEND_N X C0_RX_THRESH_INTR_REQ Receive threshold (non paced) C0_RX_THRESH_INTR_PEND X C0_RX_INTR_REQ Receive pending interrupt (paced) C0_RX_INTR_PEND X EMAC SS0 C0_TX_INTR_REQ Transmit pending interrupt (paced) C0_TX_INTR_PEND X C0_MISC_INTR_REQ Stat, Host, MDIO LINKINT or MDIO USERINT C0_MISC_INTR_PEND X C0_RX_THRESH_INTR_REQ Receive threshold (non paced) C0_RX_THRESH_INTR_PEND X C0_RX_INTR_REQ Receive pending interrupt (paced) C0_RX_INTR_PEND X EMAC SS1 C0_TX_INTR_REQ Transmit pending interrupt (paced) C0_TX_INTR_PEND X C0_MISC_INTR_REQ Stat, Host, MDIO LINKINT or MDIO USERINT C0_MISC_INTR_PEND X USBSS_INTR_REQ Queue MGR or CPPI Completion interrupt USBSS_INTR_PEND X USB0_INTR_REQ USB2.0 SS USB0_INTR_PEND X RX/TX DMA, Endpoint ready/error, or USB2.0 interrupt USB1_INTR_REQ USB1_INTR_PEND X SLV0P_SWAKEUP X USB wakeup Copyright © 2010–2011, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 141 Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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