AM3892 datasheet(138/299 Pages) TI

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AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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7.3.5

SYSCLKs

In some cases, the system clock inputs and PLL outputs are sent to the PRCM module for division and

multiplexing before being routed to the various device modules. These clock outputs from the PRCM

module are called SYSCLKs. Table 7-14 lists the main device SYSCLKs along with their maximum

supported clock frequencies. In addition, limits shown in the table may be further restricted by the clock

frequency limitations of the device modules using these clocks. Frequency data in this table is based on

device operation at 1.0 GHz for the ARM Cortex-A8. For more details on module clock frequency limits,

see Section 7.3.6.

Table 7-14. SYSCLK Frequencies

SYSCLK

FREQUENCY

DESTINATION

SYSCLK2

~1 GHz

To ARM Cortex-A8

SYSCLK4

~500 MHz

L3, OCP clock for HDVPSS, TPTCs, TPCC, DMM, Unicache clock for Media

Controller, EDMA

SYSCLK5

~250 MHz

L3, L4_HS, OCP clock for EMAC, SATA, PCIe, Media Controller, OCMC RAM

SYSCLK6

~125 MHz

L3, L4_STD, UART, I2C, SPI, SD/SDIO, TIMER, GPIO, PRCM, McASP, McBSP,

GPMC, ELM, HDMI, WDT, Mailbox, RTC, Spinlock, SmartReflex and USB.

SYSCLK8

800 MHz

DDR clock, DMM

SYSCLK23

Max 333 MHz

SGX530 OCP clock

SYSCLK24

125 MHz

GMII clock

138

Power, Reset, Clocking, and Interrupts

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