AM3892 datasheet(136/299 Pages) TI

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FREQ

Flying-Adder

Synthesizer

PFD

VCO

fvco

(

)

(

)

FREQ

PLL_CLKIN

FREQ)

Floor(M

AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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7.3.4

PLLs

The device contains four embedded PLLs (Main, Audio, Video and DDR) that provide clocks to different

parts of the system. For a high-level view of the device clock architecture, including the PLL reference

clock sources and connections, see Figure 7-4.

The reference clock for most of the PLLs comes from the DEV_CLKIN input clock. Also, each PLL

supports a bypass mode in which the reference clock can be directly passed to the PLL CLKOUT. All

device PLLs (except the DDR PLL) come-up in bypass mode after reset.

Flying-adder PLLs are used for all the on-chip PLLs. Figure 7-8 shows the basic structure of the

flying-adder PLL.

Figure 7-8. Flying-Adder PLL

The flying-adder PLL has two main components: a multi-phase PLL and the flying-adder synthesizer. The

multi-phase PLL takes an input reference clock (fr), multiplies it with factor, N, and provides a K-phase

output to the flying-adder synthesizer. The flying-adder synthesizer takes this multi-phase clock input and

produces a variable frequency clock (fs). There can be a post divider on this clock which takes in clock fs

and drives out clock fo. The frequency of the clock driven out is given by:

There can be multiple flying-adder synthesizers attached to one multi-phase PLL to generate different

frequencies. In this case, FREQ (4 bits of integer and 24 bits of fractional value) and M (1 to 255) values

can be adjusted for each clock separately, based on the frequency needed. A multi-phase PLL used in

this device has a value of K = 8.

For details on programming the device PLLs, see the PLL chapter of the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

7.3.4.1

PLL Programming Limits

When programming the PLLs, the result of the following equation must be greater than the value shown in

the corresponding PLL table (this determines if the chosen PLL frequency is a valid one).

Where:

•

PLL_CLKIN is the input clock frequency (in MHz) to the PLL before the P divider

•

Floor( ) = round down

•

M = PLL divider

•

FREQ = PLL frequency setting

•

A = 169 for all PLLs with the following exception: A = 218 for the audio PLL when its input is sourced

136

Power, Reset, Clocking, and Interrupts

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