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AM3892 Datasheet(PDF) 173 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 173 Page - Texas Instruments |
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173 / 299 page  A1 A2 MPU Differential Clock Output Buffer DDR Differential CK Input Buffers Routed as Differential Pair A3 AT Rcp Clock Parallel Terminator A1 A2 A3 AT Rcp Cac DDR_1V5 0.1 µF + – + – + – A1 A2 MPU Address/Control Output Buffer DDR Address/Control Input Buffers A3 AT Vtt Address/Control Terminator Rtt AM3894 AM3892 www.ti.com SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 Figure 8-23. CK Topology for Two DDR3 Devices Figure 8-24. ADDR_CTRL Topology for Two DDR3 Devices 8.3.2.14.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices Figure 8-25 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 8-26 shows the corresponding ADDR_CTRL routing. Copyright © 2010–2011, Texas Instruments Incorporated Peripheral Information and Timings 173 Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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