AM3892 datasheet(169/299 Pages) TI

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AM3894

AM3892

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SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

8.3.2.10 Net Classes

Table 8-22 lists the clock net classes for the DDR3 interface. Table 8-23 lists the signal net classes, and

associated clock net classes, for signals in the DDR3 interface. These net classes are used for the

termination and routing rules that follow.

Table 8-22. Clock Net Class Definitions

CLOCK NET CLASS

MPU PIN NAMES

DDR[x]_CLK[x]/DDR[x]_CLK[x]

DQS0

DDR[x]_DQS[0]/DDR[x]_DQS[0]

DQS1

DDR[x]_DQS[1]/DDR[x]_DQS[1]

DQS2(1)

DDR[x]_DQS[2]/DDR[x]_DQS[2]

DQS3(1)

DDR[x]_DQS[3]/DDR[x]_DQS[3]

(1)

Only used on 32-bit wide DDR3 memory systems.

Table 8-23. Signal Net Class Definitions

ASSOCIATED CLOCK

CLOCK NET CLASS

MPU PIN NAMES

NET CLASS

ADDR_CTRL

DDR[x]_BA[2:0], DDR[x]_A[14:0], DDR[x]_CS[x], DDR[x]_CAS, DDR[x]_RAS,

DDR[x]_WE, DDR[x]_CKE

DQ0

DQS0

DDR[x]_D[7:0], DDR[x]_DQM[0]

DQ1

DQS1

DDR[x]_D[15:8], DDR[x]_DQM[1]

DQ2(1)

DQS2

DDR[x]_D[23:16], DDR[x]_DQM[2]

DQ3(1)

DQS3

DDR[x]_D[31:24], DDR[x]_DQM[3]

(1)

Only used on 32-bit wide DDR3 memory systems.

8.3.2.11 DDR3 Signal Termination

Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by

ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in

the routing rules in the following sections.

8.3.2.12 VREFSSTL_DDR Routing

VREFSSTL_DDR (VREF) is used as a reference by the input buffers of the DDR3 memories as well as

the MPU. VREF is intended to be half the DDR3 power supply voltage and is typically generated with the

DDR3 1.5-V and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF bypass

capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing

congestion.

8.3.2.13 VTT

Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is

expected to source and sink current, specifically the termination current for the ADDR_CTRL net class

Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power

sub-plane. VTT should be bypassed near the terminator resistors.

8.3.2.14 CK and ADDR_CTRL Topologies and Routing Definition

The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew

between them. CK is a bit more complicated because it runs at a higher transition rate and is differiential.

The following subsections show the topology and routing for various DDR3 configurations for CK and

ADDR_CTRL. The figures in the following subsections define the terms for the routing specification

detailed in Table 8-24.

Peripheral Information and Timings

169

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