AM3892 datasheet(170/299 Pages) TI

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MPU

Differential Clock

Output Buffer

DDR Differential CK Input Buffers

Routed as Differential Pair

Rcp

Clock Parallel

Terminator

Rcp

Cac

DDR_1V5

0.1 µF

–

+ –

MPU

Address/Control

Output Buffer

DDR Address/Control Input Buffers

Vtt

Address/Control

Terminator

Rtt

AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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8.3.2.14.1 Four DDR3 Devices

Four DDR3 devices are supported on the DDR EMIF consisting of four x8 DDR3 devices arranged as one

bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two

pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB.

8.3.2.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices

Figure 8-17 shows the topology of the CK net classes and Figure 8-18 shows the topology for the

corresponding ADDR_CTRL net classes.

Figure 8-17. CK Topology for Four x8 DDR3 Devices

Figure 8-18. ADDR_CTRL Topology for Four x8 DDR3 Devices

8.3.2.14.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices

Figure 8-19 shows the CK routing for four DDR3 devices placed on the same side of the PCB. Figure 8-20

shows the corresponding ADDR_CTRL routing.

170

Peripheral Information and Timings

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AM3892 Datasheet(PDF) 170 Page - Texas Instruments

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