AM3892 datasheet(167/299 Pages) TI

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DDR[0] Keep Out Region

Encompasses Entire DDR[0] Routing Area

DDR3 Controllers

DDR[1] Keep Out Region

Encompasses Entire DDR[1] Routing Area

AM3894

AM3892

www.ti.com

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

Table 8-19. Placement Specifications

NO.

PARAMETER

MIN

MAX

UNIT

X1(1)(2)(3)

1000

Mils

X2(1)(2)

600

Mils

Y Offset(1)(2)(3)

1500

Mils

DDR3 keepout region

Clearance from non-DDR3 signal to DDR3 keepout region(4)(5)(6)

(1)

For dimension definitions, see Figure 8-15.

(2)

Measurements from center of MPU to center of DDR3 device.

(3)

Minimizing X1 and Y improves timing margins.

(4)

w is defined as the signal trace width.

(5)

Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.

(6)

Note that DDR3 signals from one DDR3 controller are considered non-DDR3 to the other controller. In other words, keep the two DDR3

interfaces separated by this specification.

8.3.2.7

DDR3 Keepout Region

The region of the PCB used for DDR3 circutry must be isolated from other signals. The DDR3 keepout

region is defined for this purpose and is shown in Figure 8-16. The size of this region varies with the

placement and DDR routing. Additional clearances required for the keepout region are shown in

Table 8-19. Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout

region. Non-DDR3 signals may be routed in the region, provided they are routed on layers separated from

the DDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in

this region. In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note

that the two DDR3 controller's signals should be separated from each other by the specification in

Table 8-19, item 5.

Figure 8-16. DDR3 Keepout Region

8.3.2.8

Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry.

Table 8-20 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note

that this table only covers the bypass needs of the DDR3 controllers and DDR3 device(s). Additional bulk

bypass capacitance may be needed for other circuitry. Also note that Table 8-20 is per DDR3 controller;

thus, systems using both controllers have to meet the needs of Table 8-20 twice, once for each controller.

Peripheral Information and Timings

167

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