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AM3892 Datasheet(PDF) 165 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 165 Page - Texas Instruments |
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165 / 299 page  AM3894 AM3892 www.ti.com SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 8.3.2.4 Compatible JEDEC DDR3 Devices Table 8-15 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface. Generally, the DDR3 interface is compatible with DDR3-1600 devices in the x8 or x16 widths. Table 8-15. Compatible JEDEC DDR3 Devices NO. PARAMETER MIN MAX UNIT 1 JEDEC DDR3 device speed grade(1) DDR3-800 DDR3-1600 2 JEDEC DDR3 device bit width x8 x16 Bits 3 JEDEC DDR3 device count(2) 2 8 Devices (1) DDR3 speed grade depends on desired clock rate. Data rate is 2x the clock rate. For DDR3-1600, the clock rate is 800 MHz. (2) For valid DDR3 device configurations and device counts, see Section 8.3.2.3, Figure 8-13, and Figure 8-14. 8.3.2.5 PCB Stackup The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 8-16. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI performance, or to reduce the size of the PCB footprint. A six-layer stackup is shown in Table 8-17. Complete stackup specifications are provided in Table 8-18. Table 8-16. Minimum PCB Stackup LAYER TYPE DESCRIPTION 1 Signal Top routing mostly vertical 2 Plane Split power plane 3 Plane Full ground plane 4 Signal Bottom routing mostly horizontal Table 8-17. Six-Layer PCB Stackup Suggestion LAYER TYPE DESCRIPTION 1 Signal Top routing mostly vertical 2 Plane Ground 3 Plane Split power plane 4 Plane Split power plane or Internal routing 5 Plane Ground 6 Signal Bottom routing mostly horizontal Copyright © 2010–2011, Texas Instruments Incorporated Peripheral Information and Timings 165 Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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