AM3892 datasheet(162/299 Pages) TI

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AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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8.3.2.1.1 DDR3 versus DDR2

This specification only covers AM389x MPU PCB designs that utilize DDR3 memory. Designs using DDR2

memory should use the PCB design specifications for DDR2 memory in Section 8.3.1. While similar, the

two memory systems have different requirements. It is currently not possible to design one PCB that

covers both DDR2 and DDR3.

8.3.2.2

DDR3 Device Combinations

Since there are several possible combinations of device counts and single- or dual-side mounting,

Table 8-14 summarizes the supported device configurations.

Table 8-14. Supported DDR3 Device Combinations(1)

NUMBER OF DDR3 DEVICES

DDR3 DEVICE WIDTH (BITS)

MIRRORED?

DDR3 EMIF WIDTH (BITS)

Y(2)

Y(3)

(1)

This table is per EMIF.

(2)

Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of

the board.

(3)

This is two mirrored pairs of DDR3 devices.

8.3.2.2.1 DDR3 EMIFs

The MPU contains two separate DDR3 EMIFs. This specification covers one of these EMIFs (DDR[0])

and, thus, needs to be implemented twice, once for each EMIF. The PCB layout generally turns out to be

a semi-mirror with DDR[1] being a flipped version of DDR[0]; the only exception being the DDR3 devices

themselves are not flipped unless mounted on opposite sides of the PCB. Requirements are identical

between the two EMIFs.

8.3.2.3

DDR3 Interface Schematic

8.3.2.3.1 32-Bit DDR3 Interface

The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width

of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR

devices look like two 8-bit devices. Figure 8-13 and Figure 8-14 show the schematic connections for 32-bit

interfaces using x16 devices.

8.3.2.3.2 16-Bit DDR3 Interface

Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see Figure 8-13

and Figure 8-14); only the high-word DDR memories are removed and the unused DQS inputs are tied off.

The MPU DDR[x]_DQS[2] and DDR[x]_DQS[3] pins should be pulled to the DDR supply via 1-k

resistors. Similarly, the DDR[x]_DQS[2] and DDR[x]_DQS[3] pins should be pulled to ground via 1-k

resistors.

When not using a DDR interface, the proper method of handling the unused pins is to tie off the DQS pins

by pulling the non-inverting DQS pin to the DDR_1V5 supply via a 1k-

Ω resistor and pulling the inverting

DQSn pin to ground via a 1k-

Ω resistor. This needs to be done for each byte not used. Also, include the

50-

Ω pulldown for DDR[x]_VTP. All other DDR interface pins can be left unconnected. Note that the

supported modes for use of the DDR EMIF are 32 bits wide, 16 bits wide, or not used.

162

Peripheral Information and Timings

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