AM3892 datasheet(159/299 Pages) TI

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DDR2 Device

DDR2 Controller

VREF Bypass Capacitor

VREF Nominal Max Trace

width is 20 mils

Neck down to minimum in BGA escape

regions is acceptable. Narrowing to

accomodate via congestion for short

distances is also acceptable. Best

performance is obtained if the width

of VREF is maximized.

AM3894

AM3892

www.ti.com

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

Table 8-9. Signal Net Class Definitions

ASSOCIATED CLOCK

CLOCK NET CLASS

MPU PIN NAMES

NET CLASS

ADDR_CTRL

DDR[x]_BA[2:0], DDR[x]_A[14:0], DDR[x]_CS[x], DDR[x]_CAS, DDR[x]_RAS,

DDR[x]_WE, DDR[x]_CKE

DQ0

DQS0

DDR[x]_D[7:0], DDR[x]_DQM[0]

DQ1

DQS1

DDR[x]_D[15:8], DDR[x]_DQM[1]

DQ2(1)

DQS2

DDR[x]_D[23:16], DDR[x]_DQM[2]

DQ3(1)

DQS3

DDR[x]_D[31:24], DDR[x]_DQM[3]

(1)

Only used on 32-bit wide DDR2 memory systems.

8.3.1.2.9 DDR2 Signal Termination

Signal terminators are required in CK and ADDR_CTRL net classes. Serial terminators may be used on

data lines to reduce EMI risk; however, serial terminations are the only type permitted. ODT's are

integrated on the data byte net classes. They should be enabled to ensure signal integrity.Table 8-10

shows the specifications for the series terminators.

Table 8-10. DDR2 Signal Terminations

No.

Parameter

Min

Typ

Max

Unit

CK net class(1)

Ω

ADDR_CTRL net class(1)(2)(3)

Ω

Data byte net classes (DQS0-DQS3, DQ0-DQ3)(1)(2)(3)(4)

Ω

(1)

Only series termination is permitted, parallel or SST specifically disallowed on board.

(2)

Terminator values larger than typical only recommended to address EMI issues.

(3)

Termination value should be uniform across net class.

(4)

Only required for GMI reduction.

8.3.1.2.10 VREFSSTL_DDR Routing

VREFSSTL_DDR is used as a reference by the input buffers of the DDR2 memories as well as the MPU.

VREF is intended to be half the DDR2 power supply voltage and should be created using a resistive

divider as shown in Figure 8-6. Other methods of creating VREF are not recommended. Figure 8-9 shows

the layout guidelines for VREF.

Figure 8-9. VREF Routing and Topology

Peripheral Information and Timings

159

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