AM3892 datasheet(157/299 Pages) TI

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DDR2 Device

AM3894

AM3892

www.ti.com

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

8.3.1.2.5 DDR2 Keepout Region

The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2

keepout region is defined for this purpose and is shown in Figure 8-8. The size of this region varies with

the placement and DDR routing. Additional clearances required for the keepout region are shown in

Table 8-5.

Figure 8-8. DDR2 Keepout Region

NOTE

The region shown in should encompass all the DDR2 circuitry and varies depending on

placement. Non-DDR2 signals should not be routed on the DDR signal layers within the

DDR2 keepout region. Non-DDR2 signals may be routed in the region, provided t hey are

routed on layers separated from DDR2 signal layers by a ground layer. No breaks should be

allowed in the reference ground layers in this region. In addition, the 1.8V power plane

should cover the entire keepout region. Routes for the two DDR interfaces must be

separated by at least 4x; the more separation, the better.

8.3.1.2.6 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.

Table 8-6 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note

that this table only covers the bypass needs of the DDR2 interfaces and DDR2 device. Additional bulk

bypass capacitance may be needed for other circuitry.

Table 8-6. Bulk Bypass Capacitors

No.

Parameter

Min

Max

Unit

DVDD18 bulk bypass capacitor count(1)

Devices

DVDD18 bulk bypass total capacitance

μF

DDR#1 bulk bypass capacitor count(1)

Devices

DDR#1 bulk bypass total capacitance(1)

μF

DDR#2 bulk bypass capacitor count(2)

Devices

DDR#2 bulk bypass total capacitance(1)(2)

μF

(1)

These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed

(HS) bypass capacitors. Use half of these capacitors for DDR[0] and half for DDR[1].

(2)

Only used on 32-bit wide DDR2 memory systems.

Peripheral Information and Timings

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