AM3892 datasheet(206/299 Pages) TI

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AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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8.8

General-Purpose Memory Controller (GPMC) and Error Locator Module (ELM)

The GPMC is a device memory controller used to provide a glueless interface to external memory devices

such as NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection for 8-bit or 16-bit NAND

Flash), SRAM, and Pseudo-SRAM. It includes flexible asynchronous protocol control for interface to

SRAM-like memories and custom logic (FPGA, CPLD, ASICs, etc.).

Other supported features include:

•

8-/16-bit wide multiplexed address/data bus

•

Up to 6 chip selects with up to 256M-byte address space per chip select pin

•

Non-multiplexed address/data mode

•

Pre-fetch and write posting engine associated with system DMA to get full performance from NAND

device with minimum impact on NOR/SRAM concurrent access.

The device also contains an Error Locator Module (ELM) which is used to extract error addresses from

syndrome polynomials generated using a BCH algorithm. Each of these polynomials gives a status of the

read operations for a 512 bytes block from a NAND flash and its associated BCH parity bits, plus

optionally spare area information. The ELM has the following features:

•

4-bit, 8-bit, and 16-bit per 512-byte block error location based on BCH algorithms

•

Eight simultaneous processing contexts

•

Page-based and continuous modes

•

Interrupt generation on error location process completion

–

When the full page has been processed in page mode

–

For each syndrome polynomial in continuous mode.

For more detailed information on the GPMC, see the GPMC chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

8.8.1

GPMC and ELM Peripheral Register Descriptions

Table 8-52. GPMC Registers(1)(2)

HEX ADDRESS

ACRONYM

0x5000 0000

GPMC_REVISION

GPIO Revision

0x5000 0010

GPMC_SYSCONFIG

System Configuration

0x5000 0014

GPMC_SYSSTATUS

System Status

0x5000 0018

GPMC_IRQSTATUS

Status for Interrupt

0x5000 001C

GPMC_IRQENABLE

Interrupt Enable

0x5000 0040

GPMC_TIMEOUT_CONTROL

Timeout Counter Start Value

0x5000 0044

GPMC_ERR_ADDRESS

Error Address

0x5000 0048

GPMC_ERR_TYPE

Error Type

0x5000 0050

GPMC_CONFIG

GPMC Global Configuration

0x5000 0054

GPMC_STATUS

GPMC Global Status

0x5000 0060 + (0x0000 0030 * i)

GPMC_CONFIG1_0 -

Parameter Configuration 1_0-5

GPMC_CONFIG1_5

0x5000 0064 + (0x0000 0030 * i)

GPMC_CONFIG2_0 -

Parameter Configuration 2_0-5

GPMC_CONFIG2_5

0x5000 0068 + (0x0000 0030 * i)

GPMC_CONFIG3_0 -

Parameter Configuration 3_0-5

GPMC_CONFIG3_5

0x5000 006C + (0x0000 0030 * i)

GPMC_CONFIG4_0 -

Parameter Configuration 4_0-5

GPMC_CONFIG4_5

0x5000 0070 + (0x0000 0030 * i)

GPMC_CONFIG5_0 -

Parameter Configuration 5_0-5

GPMC_CONFIG5_5

(1)

i = 0 to 5.

(2)

j = 0 to 8.

206

Peripheral Information and Timings

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