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AM3894

AM3892

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SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

8.7

General-Purpose Input/Output (GPIO)

The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.

When configured as an output, a write to an internal register controls the state driven on the output pin.

When configured as an input, the state of the input is detectable by reading the state of an internal

modes. The GPIO peripheral provides generic connections to external devices.

The device contains two GPIO modules and each GPIO module is made up of 32 identical channels.

The device GPIO peripheral supports the following:

•

Up to 64 3.3-V GPIO pins, GP0[31:0] and GP1[31:0] (the exact number available varies as a function

of the device configuration). Each channel can be configured to be used in the following applications:

–

Data input/output

–

Keyboard interface with a de-bouncing cell

–

Synchronous interrupt generation (in active mode) upon the detection of external events (signal

transition(s) and/or signal level(s)).

•

Synchronous interrupt requests from each channel are processed by two identical interrupt generation

sub-modules to be used independently by the ARM. Interrupts can be triggered by rising and/or falling

edge, specified for each interrupt-capable GPIO signal.

•

Shared registers can be accessed through "Set & Clear" protocol. Software writes 1 to corresponding

bit position(s) to set or to clear GPIO signal(s). This allows multiple software processes to toggle GPIO

output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts,

to prevent context switching to another process during GPIO programming).

•

Separate input/output registers.

•

Output register in addition to set/clear so that, if preferred by software, some GPIO output signals can

be toggled by direct write to the output register(s).

•

Output register, when read, reflects output drive status. This, in addition to the input register reflecting

pin status and open-drain I/O cell, allows wired logic to be implemented.

For more detailed information on GPIOs, see the GPIO chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

8.7.1

GPIO Peripheral Register Descriptions

Table 8-49. GPIO Registers

GPIO0 HEX ADDRESS

GPIO1 HEX ADDRESS

ACRONYM

0x4803 2000

0x4804 C000

GPIO_REVISION

GPIO Revision

0x4803 2010

0x4804 C010

GPIO_SYSCONFIG

System Configuration

0x4803 2020

0x4804 C020

GPIO_EOI

End of Interrupt

0x4803 2024

0x4804 C024

GPIO_IRQSTATUS_RAW_0

Status Raw for Interrupt 1

0x4803 2028

0x4804 C028

GPIO_IRQSTATUS_RAW_1

Status Raw for Interrupt 2

0x4803 202C

0x4804 C02C

GPIO_IRQSTATUS_0

Status for Interrupt 1

0x4803 2030

0x4804 C030

GPIO_IRQSTATUS_1

Status for Interrupt 2

0x4803 2034

0x4804 C034

GPIO_IRQSTATUS_SET_0

Enable Set for Interrupt 1

0x4803 2038

0x4804 C038

GPIO_IRQSTATUS_SET_1

Enable Set for Interrupt 2

0x4803 203C

0x4804 C03C

GPIO_IRQSTATUS_CLR_0

Enable Clear for Interrupt 1

0x4803 2040

0x4804 C040

GPIO_IRQSTATUS_CLR_1

Enable Clear for Interrupt 2

0x4803 2044

0x4804 C044

GPIO_IRQWAKEN_0

Wakeup Enable for Interrupt 1

0x4803 2048

0x4804 C048

GPIO_IRQWAKEN_1

Wakeup Enable for Interrupt 2

0x4803 2114

0x4804 C114

GPIO_SYSSTATUS

System Status

0x4803 2130

0x4804 C130

GPIO_CTRL

Module Control

0x4803 2134

0x4804 C134

GPIO_OE

Output Enable

Peripheral Information and Timings

203

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