AM3892 datasheet(256/299 Pages) TI

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AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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8.13 Multichannel Buffered Serial Port (McBSP)

The McBSP provides these functions:

•

Full-duplex communication

•

Double-buffered data registers, which allow a continuous data stream

•

Independent framing and clocking for receive and transmit

•

Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially

connected analog-to-digital (A/D) and digital-to-analog (D/A) devices

•

Supports TDM, I2S, and similar formats

•

External shift clock or an internal, programmable frequency shift clock for data transfer

•

5KB Tx and Rx buffer

•

Supports three interrupt and two DMA requests.

The McBSP module may support two types of data transfer at the system level:

•

The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge

and captured on the same edge (one clock period later).

•

The half-cycle mode, for which one half clock period is used to transfer the data, generated on one

edge and captured on the opposite edge (one half clock period later). Note that a new data is

generated only every clock period, which secures the required hold time. The interface clock

(CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be configured

accordingly with the external peripheral (activation edge capability) and the type of data transfer

required at the system level.

For more detailed information on the McBSP peripheral, see the McBSP chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

The following sections describe the timing characteristics for applications in normal mode (that is, the

McBSP connected to one peripheral) and TDM applications in multipoint mode.

8.13.1 McBSP Peripheral Register Descriptions

Table 8-80. McBSP Registers(1)

HEX ADDRESS

ACRONYM

0x4700 0000

DRR_REG

McBSP data receive

0x4700 0008

DXR_REG

McBSP data transmit

0x4700 0010

SPCR2_REG

McBSP serial port control 2

0x4700 0014

SPCR1_REG

McBSP serial port control 1

0x4700 0018

RCR2_REG

McBSP receive control 2

0x4700 001C

RCR1_REG

McBSP receive control 1

0x4700 0020

XCR2_REG

McBSP transmit control 2

0x4700 0024

XCR1_REG

McBSP transmit control 1

0x4700 0028

SRGR2_REG

McBSP sample rate generator 2

0x4700 002C

SRGR1_REG

McBSP sample rate generator 1

0x4700 0030

MCR2_REG

McBSP multichannel 2

0x4700 0034

MCR1_REG

McBSP multichannel 1

0x4700 0038

RCERA_REG

McBSP receive channel enable partition A

0x4700 003C

RCERB_REG

McBSP receive channel enable partition B

0x4700 0040

XCERA_REG

McBSP transmit channel enable partition A

0x4700 0044

XCERB_REG

McBSP transmit channel enable partition B

0x4700 0048

PCR_REG

McBSP pin control

0x4700 004C

RCERC_REG

McBSP receive channel enable partition C

(1)

Note that the McBSP registers are 32-bit aligned.

256

Peripheral Information and Timings

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