AM3892 datasheet(260/299 Pages) TI

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AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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8.14 Peripheral Component Interconnect Express (PCIe)

The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus

interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. The device

implements a single two-lane PCIe 2.0 (5.0 GT/s) endpoint/root complex port.

The device PCIe supports the following features:

•

Supports Gen1/Gen2 in x1 or x2 mode

•

One port with up to 2 x 5 GT/s lanes

•

Single virtual channel (VC), single traffic class (TC)

•

Single function in end-point mode

•

Automatic width and speed negotiation and lane reversal

•

Max payload: 128 byte outbound, 256 byte inbound

•

Automatic credit management

•

ECRC generation and checking

•

Configurable BAR filtering

•

Supports PCIe messages

•

Legacy interrupt reception (RC) and generation (EP)

•

MSI generation and reception

•

PCI device power management, except D3 cold with vaux

•

Active state power management state L0 and L1.

For more detailed information on the PCIe port peripheral module, see the PCIe chapter in the AM38x

Sitara ARM Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

The PCIe peripheral on the device conforms to the PCI Express Base 2.0 Specification.

8.14.1 PCIe Design and Layout Guidelines

8.14.1.1 Clock Source

A standard 100-MHz PCIe differential clock source must be used for PCIe operation (for details, see

Section 7.3.2).

8.14.1.2 PCIe Connections and Interface Compliance

The PCIe interface on the device is compliant with the PCI Express Base 2.0 Specification. Refer to the

PCIe specifications for all connections that are described in it. For coupling capacitor selection, see

Section 8.14.1.2.1.

The use of PCIe-compatible bridges and switches is allowed for interfacing with more than one other

processor or PCIe device.

8.14.1.2.1 Coupling Capacitors

AC coupling capacitors are required on the transmit data pair. Table 8-85 shows the requirements for

these capacitors.

Table 8-85. AC Coupling Capacitors Requirements

PARAMETER

MIN

TYP

MAX

UNIT

PCIe AC coupling capacitor value

200

PCIe AC coupling capacitor package size(1)

0402

0603

EIA(2)

(1)

The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair, placed side by side.

(2)

EIA LxW units; i.e., a 0402 is a 40x20 mil (thousandths of an inch) surface-mount capacitor.

260

Peripheral Information and Timings

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