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AM3892 Datasheet(PDF) 263 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 263 Page - Texas Instruments |
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263 / 299 page  AM3894 AM3892 www.ti.com SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 Table 8-88. PCIe Registers (continued) HEX ADDRESS ACRONYM REGISTER NAME 0x5100 0184 IRQ_STATUS Interrupt Enabled Status 0x5100 0188 IRQ_ENABLE_SET Interrupt Enable Set 0x5100 018C IRQ_ENABLE_CLR Interrupt Enable Clear 0x5100 01C0 ERR_IRQ_STATUS_RAW Raw ERR Interrupt Status 0x5100 01C4 ERR_IRQ_STATUS ERR Interrupt Enabled Status 0x5100 01C8 ERR_IRQ_ENABLE_SET ERR Interrupt Enable Set 0x5100 01CC ERR_IRQ_ENABLE_CLR ERR Interrupt Enable Clear 0x5100 01D0 PMRST_IRQ_STATUS_RAW Power Management and Reset Interrupt Status 0x5100 01D4 PMRST_IRQ_STATUS Power Management and Reset Interrupt Enabled Status 0x5100 01D8 PMRST_ENABLE_SET Power Management and Reset Interrupt Enable Set 0x5100 01DC PMRST_ENABLE_CLR Power Management and Reset Interrupt Enable Clear 0x5100 0200 OB_OFFSET_INDEXn Outbound Translation Region N Offset Low and Index 0x5100 0204 OB_OFFSETn_HI Outbound Translation Region N Offset High 0x5100 0300 IB_BAR0 Inbound Translation Bar Match 0 0x5100 0304 IB_START0_LO Inbound Translation 0 Start Address Low 0x5100 0308 IB_START0_HI Inbound Translation 0 Start Address High 0x5100 030C IB_OFFSET0 Inbound Translation 0 Address Offset 0x5100 0310 IB_BAR1 Inbound Translation Bar Match 1 0x5100 0314 IB_START1_LO Inbound Translation 1 Start Address Low 0x5100 0318 IB_START1_HI Inbound Translation 1 Start Address High 0x5100 031C IB_OFFSET1 Inbound Translation 1 Address Offset 0x5100 0320 IB_BAR2 Inbound Translation Bar Match 2 0x5100 0324 IB_START2_LO Inbound Translation 2 Start Address Low 0x5100 0328 IB_START2_HI Inbound Translation 2 Start Address High 0x5100 032C IB_OFFSET2 Inbound Translation 2 Address Offset 0x5100 0330 IB_BAR3 Inbound Translation Bar Match 3 0x5100 0334 IB_START3_LO Inbound Translation 3 Start Address Low 0x5100 0338 IB_START3_HI Inbound Translation 3 Start Address High 0x5100 033C IB_OFFSET3 Inbound Translation 3 Address Offset 0x5100 0380 PCS_CFG0 PCS Configuration 0 0x5100 0384 PCS_CFG1 PCS Configuration 1 0x5100 0388 PCS_STATUS PCS Status 0x5100 0390 SERDES_CFG0 SerDes Configuration for Lane 0 0x5100 0394 SERDES_CFG1 SerDes Configuration for Lane 1 8.14.3 PCIe Electrical Data/Timing Texas Instruments (TI) has performed the simulation and system characterization to ensure that the PCIe peripheral meets all AC timing specifications as required by the PCI Express Base 2.0 Specification. Therefore, the AC timing specifications are not reproduced here. For more information on the AC timing specifications, see Sections 4.3.3.5 and 4.3.4.4 of the PCI Express Base 2.0 Specification. Copyright © 2010–2011, Texas Instruments Incorporated Peripheral Information and Timings 263 Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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