AM3892 datasheet(261/299 Pages) TI

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AM3894

AM3892

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SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

8.14.1.2.2 Polarity Inversion

The PCIe specification requires polarity inversion support. This means, for layout purposes, polarity is

unimportant since each signal can change its polarity on-die inside the chip. This means polarity within a

lane is unimportant for layout.

8.14.1.2.3 Lane Reversal

The device supports lane reversal. Since there are two lanes, this means the lanes can be switched in

layout for better PCB routing.

8.14.1.3 Non-Standard PCIe Connections

The following sections contain suggestions for any PCIe connection that is not described in the official

PCIe specification, such as an on-board device-to-device connection, or device-to-other PCIe-compliant

processor connection.

8.14.1.3.1 PCB Stackup Specifications

Table 8-86 shows the stackup and feature sizes required for these types of PCIe connections.

Table 8-86. PCIe PCB Stackup Specifications

PARAMETER

MIN

TYP

MAX

UNIT

PCB Routing/Plane Layers

Layers

Signal Routing Layers

Layers

Number of ground plane cuts allowed within PCIe routing region

Cuts

Number of layers between PCIe routing area and reference plane(1)

Layers

PCB Routing clearance

Mils

PCB Trace width(2)

Mils

PCB BGA escape via pad size

Mils

PCB BGA escape via hole size

Mils

MPU BGA pad size(3)(4)

0.4

(1)

A reference plane may be a ground plane or the power plane referencing the PCIe signals.

(2)

In breakout area.

(3)

Non-solder mask defined pad.

(4)

Per IPC-7351A BGA pad size guideline.

8.14.1.3.2 Routing Specifications

The PCIe data signal traces must be routed to achieve 100

Ω (±20%) differential impedance and 60 Ω

(±15%) single-ended impedance. The single-ended impedance is required because differential signals are

extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important.

These requirements are the same as those recommended in the PCIe Motherboard Checklist 1.0

document, available from PCI-SIG.

These impedances are impacted by trace width, trace spacing, distance between signals and referencing

planes, and dielectric material. Verify with a PCB design tool that the trace geometry for both data signal

pairs result in as close to 100

Ω differential impedance and 60 Ω single-ended impedance as possible. For

best accuracy, work with your PCB fabricator to ensure this impedance is met.

In general, closely coupled differential signal traces are not an advantage on PCBs. When differential

signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing

variations affect impedance dramatically, so tight impedance control can be more problematic to maintain

in production.

Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing

make obstacle avoidance easier, and trace width variations do not affect impedance as much; therefore, it

is easier to maintain an accurate impedance over the length of the signal. The wider traces also show

reduced skin effect and, therefore, often result in better signal integrity.

Peripheral Information and Timings

261

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