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90E21 Datasheet(PDF) 48 Page - Integrated Device Technology |
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90E21 Datasheet(HTML) 48 Page - Integrated Device Technology |
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48 / 57 page  90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Electrical Specification 48 January 10, 2012 6 ELECTRICAL SPECIFICATION 6.1 ELECTRICAL SPECIFICATION Parameters and Description Min. Typical Max. Unit Test Conditions and Comments Accuracy DC Power Supply Rejection Ratio (PSRR) ± 0.1 % VDD=3.3V±0.3V, 100Hz, I=5A, V=220V, L line shunt resistor 150 µΩ, N line CT 1000:1, sampling resistor 4.8 Ω AC Power Supply Rejection Ratio (PSRR) ± 0.1 % VDD=3.3V superimposes 400mVrms, 100Hz Sinu- soidal signal, I=5A, V=220V, L line shunt resistor 150 µΩ, N line CT 1000:1, sampling resistor 4.8Ω Active Energy Error (Dynamic Range 5000:1) ± 0.1 % L line current gain is ‘24’; N line current gain is ‘1’ Channel Characteristics Sampling Frequency 8kHz L Line Current Channel Equivalent Input Noise 19.1 Single side band noise (measured at 50Hz, and PGA gain is ‘24’) N Line Current Channel Equivalent Input Noise 458.4 Single side band noise (measured at 50Hz, and PGA gain is ‘1’) Voltage Channel Equivalent Input Noise 458.4 Single side band noise (measured at 50Hz, and PGA gain is ‘1’) Total Harmonic Distortion for Each Channel 80 dB 25°C, PGA gain is ‘1’, 500mVrms input Reactive Energy Metering Bandwidth 4 kHz Active Energy Metering Bandwidth 4 kHz Irms and Vrms Measurement Bandwidth 4 kHz Measurement Error ± 0.5 % Analog Input L Line Current Channel Differential Input 5 µ 25m Vrms PGA gain is ‘24’ 7.5 µ 37.5m PGA gain is ‘16’ 15 µ 75m PGA gain is ‘8’ 30 µ 150m PGA gain is ‘4’ 120 µ 600m PGA gain is ‘1’ N Line Current Channel Differential Input 30 µ 150m Vrms PGA gain is ‘4’ 60 µ 300m PGA gain is ‘2’ 120 µ 600m PGA gain is ‘1’ Voltage Channel Differential Input 120 µ 600m Vrms PGA gain is ‘1’ L Line Current Channel Input Impedance 1 K Ω N Line Current Channel Input Impedance 50 K Ω Voltage Channel Input Impedance 50 K Ω L Line Current Channel DC Offset 10 mV PGA gain is ‘24’ N Line Current Channel DC Offset 10 mV PGA gain is ‘1’ Voltage Channel DC Offset 10 mV PGA gain is ‘1’ Reference On-Chip Reference (90E21/22/23/24) 1.398 1.417 1.440 V Reference voltage test mode Reference Voltage Temperature Coefficient ± 15 ± 40 ppm/°C Clock Crystal or External Clock 8.192 MHz The Accuracy of crystal or external clock is ±100 ppm SPI Interface SPI Interface Bit Rate 200 160k bps Pulse Width CFx Pulse Width 80 ms If T ≥ 160 ms, width=80ms; if T<160 ms, width = 0.5T. Refer to Section 6.6 ESD Machine Model (MM) 400 V JESD22-A115 Charged Device Model (CDM) 1000 V JESD22-C101 Hz / nV Hz / nV Hz / nV |
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