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90E21 Datasheet(PDF) 17 Page - Integrated Device Technology |
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90E21 Datasheet(HTML) 17 Page - Integrated Device Technology |
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17 / 57 page ![]() 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Interface 17 January 10, 2012 4.1.2 THREE-WIRE MODE In three-wire mode, CS is always at low level. When there is no oper- ation, SCLK keeps at high level. The start of a read or write operation is triggered if SCLK is consistently low for at least 400 µs. The subsequent read or write operation is similar to that in four-wire mode. Refer to Fig- ure-8 and Figure-9. Figure-8 Read Sequence in Three-Wire Mode Figure-9 Write Sequence in Three-Wire Mode CS SCLK 10 123456789 11 12 13 14 15 16 17 18 19 20 21 22 23 Register address 24 1234 Low ≥ 400 µs Drive Low SDI SDO A0 A6 A5 A4 A3 A2 A1 Hign Impedance D 15 Don't care 16-bit data D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 0 D 1 Don’t care A6 A5 A4 High Impedance Low ≥ 400 µs CS SCLK SDI SDO 10 12 3 4567 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 A0 A6 A5 A4 A3 A2 A1 16-bit data High Impedance D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 Register Address D 14 D 15 24 D 13 D 12 D 11 D 10 D 9 D 8 1234 A6 A5 A4 Don't care Drive low Low ≥ 400 µs Low ≥ 400 µs Don't care |
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