90E21 datasheet(16/57 Pages) IDT

16 / 57 page

90E21/22/23/24

SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC

Interface

January 10, 2012

4INTERFACE

4.1

SERIAL PERIPHERAL INTERFACE (SPI)

SPI is a full-duplex, synchronous channel. There are two SPI modes:

four-wire mode and three-wire mode. In four-wire mode, four pins are

used: CS, SCLK, SDI and SDO. In three-wire mode, three pins are

used: SCLK, SDI and SDO. Data on SDI is shifted into the chip on the

rising edge of SCLK while data on SDO is shifted out of the chip on the

falling edge of SCLK. The LastSPIData register (06H) stores the 16-bit

data that is just read or written.

4.1.1

FOUR-WIRE MODE

In four-wire mode, the CS pin must be driven low for the entire read

or write operation. The first bit on SDI defines the access type and the

lower 7-bit is decoded as address.

Read Sequence

As shown in Figure-6, a read operation is initiated by a high on SDI

followed by a 7-bit register address. A 16-bit data in this register is then

shifted out of the chip on SDO. A complete read operation contains 24

cycles.

Figure-6 Read Sequence in Four-Wire Mode

Write Sequence

As shown in Figure-7, a write operation is initiated by a low on SDI

followed by a 7-bit register address. A 16-bit data is then shifted into the

chip on SDI. A complete write operation contains 24 cycles.

Figure-7 Write Sequence in Four-Wire Mode

SCLK

SDI

SDO

1234

6789

High Impedance

D15

Don't care

16-bit data

D14 D13 D12 D11 D10 D9

D7 D6

D4 D3 D2

SCLK

SDI

SDO

6789

16-bit data

High Impedance

D15

D14D13 D12D11 D10 D9

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