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90E21 Datasheet(PDF) 51 Page - Integrated Device Technology |
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90E21 Datasheet(HTML) 51 Page - Integrated Device Technology |
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51 / 57 page ![]() 90E21/22/23/24 SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Electrical Specification 51 January 10, 2012 6.3 POWER ON RESET TIMING Figure-12 Power On Reset Timing Diagram 6.4 ZERO-CROSSING TIMING Figure-13 Zero-Crossing Timing Diagram tDW Minimum Data Width 30T+10 ns tPD Output Delay 14T 15T+20 ns tDF note 1 Output Disable Time 16T+20 ns Note: 1. Not applicable for three-wire SPI. 2. T means SCLK cycle. T=122ns. (Typical value for four-wire SPI) Table-12 SPI Timing Specification (Continued) Table-13 Power On Reset Specification Symbol Description Min. Typical Max. Unit VH Power On Trigger Voltage 2.47 2.6 2.73 V VL Power Off Trigger Voltage 2.185 2.3 2.415 V VH-VL Hysteretic Voltage Difference 0.285 0.3 0.315 V T1 Delay Time After Power On 5 ms T2 Delay Time After Power Off 10 µs DVDD RESET T 1 V H T 2 V L ZX (Positive zero-crossing) ZX (Negative zero-crossing) ZX (All zero-crossing) T ZX T D V |
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