OR3C80 datasheet(83/210 Pages) AGERE

83 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Programmable Clock Manager (PCM)

(continued)

PCM Applications

The applications discussed below are only a small

sampling of the possible uses for the PCM. Check the

Lucent Technologies

ORCA FPGA Internet website

(listed at the end of this data sheet) for additional appli-

cation notes.

Clock Phase Adjustment

The PCM may be used to adjust the phase of the input

clock. The result is an output clock which has its active

edge either preceding or following the active edge of

the input clock. Clock phase adjustment is accom-

plished in DLL mode by delaying the clock. This is dis-

cussed in the Delay-Locked Loop (DLL) Mode section.

Examples of using the delayed clock as an early or late

phase-adjusted clock are outlined in the following para-

graphs.

An output clock that precedes the input clock can be

used to compensate for clock delay that is largely due

to excessive loading. The preceding output clock is

really not early relative to the input clock, but is delayed

almost a full cycle. This is shown in Figure 48A. The

amount of delay that is being compensated for, plus

clock setup time and some margin, is the amount less

than one full clock cycle that the output clock is delayed

from the input clock.

In some systems, it is desirable to operate logic from

several clocks that operate at different phases. This

technique is often used in microprocessor-based sys-

tems to transfer and process data synchronously

between functional areas, but without incurring exces-

sive delays. Figure 48B shows an input clock and an

output clock operating 180° out of phase. It also shows

a version of the input clock that was shifted approxi-

mately 180° using logic gates to create an inverter.

Note that the inverted clock is really shifted more than

180° due to the propagation delay of the inverter. The

PCM

output clock does not suffer from this delay. Addi-

tionally, the 180° shifted PCM output could be shifted

by some smaller amount to effect an early 180° shifted

clock that also accounts for loading effects.

In terms of degrees of phase shift, the phase of a clock

is adjustable in DLL mode with resolution relative to the

delay increment (see Table 27):

Phase Adjustment = (Delay)* 11.25,

Delay < 16

Phase Adjustment = ((Delay)* 11.25) – 360,

Delay > 16

5-5979(F)

Figure 48. Clock Phase Adjustment Using the PCM

INPUT CLOCK

OUTPUT CLOCK

INPUT CLOCK

PCM OUTPUT CLOCK

INVERTED INPUT CLOCK

A. Generating an Early Clock

B. Multiphase Clock Generation Using the DLL

UNINTENDED PHASE

SHIFT DUE TO

INVERTER DELAY

DLL DELAY

CLOCK DELAY AND SETUP

BEING COMPENSATED

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