OR3C80 datasheet(91/210 Pages) AGERE

91 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Configuration Data Format (continued)

The length and number of data frames and information on the PROM size for the Series 3 FPGAs are given in

Table 33.

Table 33. Configuration Frame Size

Bit Stream Error Checking

There are three different types of bit stream error checking performed in the

ORCA Series 3 FPGAs:

ID frame, frame alignment, and CRC checking.

The ID data frame is sent to a dedicated location in the FPGA. This ID frame contains a unique code for the device

for which it was generated. This device code is compared to the internal code of the FPGA. Any differences are

flagged as an ID error. This frame is automatically created by the bit stream generation program in

ORCA Foundry.

Each data and address frame in the FPGA begins with a frame start pair of bits and ends with eight stop bits set to

1. If any of the previous stop bits were a 0 when a frame start pair is encountered, it is flagged as a frame align-

ment error.

Error checking is also done on the FPGA for each frame by means of a checksum byte. If an error is found on eval-

uation of the checksum byte, then a checksum/parity error is flagged. The checksum is the XOR of all the data

bytes, from the start of frame up to and including the bytes before the checksum. It applies to the ID, address, and

data frames.

When any of the three possible errors occur, the FPGA is forced into an idle state, forcing INIT low. The FPGA will

remain in this state until either the RESET or PRGM pins are asserted.

If using either of the MPI modes to configure the FPGA, the specific type of bit stream error is written to one of the

MPI

registers by the FPGA configuration logic. The PGRM bit of the MPI control register can also be used to reset

out of the error condition and restart configuration.

Devices

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

# of Frames

856

984

1240

1496

1880

Data Bits/Frame

202

232

292

352

442

Configuration Data (# of frames x # of data

bits/frame)

172,912

228,288

362,080

526,592

830,960

Maximum Total # Bits/Frame (align bits, 01

frame start, 8-bit checksum, 8 stop bits)

224

256

312

376

464

Maximum Configuration Data (# bits/frame

x # of frames)

191,744

251,904

386,880

562,496

872,320

Maximum PROM Size (bits)

(add configuration header and postamble)

191,912

252,072

387,048

562,664

872,488

OR3C80 Datasheet(PDF) 91 Page - Agere Systems

OR3C80 Datasheet(HTML) 91 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL