OR3C80 datasheet(47/210 Pages) AGERE

47 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

High-Level Routing Resources

The high-level routing resources in the

ORCA Series 3 devices are interquad routing, corner cell routing, and PIC

interquad routing. These resources and their related structures are discussed in the following subsections.

Interquad Routing

In the

ORCA Series 3 devices, the PLC array is split into four equal quadrants. In between these quadrants, routing

has been added to route signals between the quadrants and distribute clocks. In addition to general routing, there

are four specialized clock routing spines. The general routing is discussed below, followed by the special clock rout-

ing.

One of the main purposes of interquad routing is to distribute internally generated signals, such as clocks and con-

trol signals. There are two types of interquad blocks: vertical and horizontal. Vertical interquad blocks (vIQ) run

between quadrants on the left and right, while horizontal interquad blocks (hIQ) run between top and bottom quad-

rants. Interquad lines begin and end in the MID cells that are discussed later. Since hIQ and vIQ blocks have the

same logic, only the hIQ block is described below. The interquad routing connects to x5 and xH segments. It does

not affect other local routing (xsw, x1, fast carry), so local routing is the same, whether PLC-PLC connections cross

quadrants or not. Figure 28 presents a (not to scale) view of interquad routing.

5-4538(F)

Figure 28. Interquad Routing

TMID

BMID

LMID

RMID

hIQ7[4:0]

hIQ5[4:0]

hIQ3[4:0]

hIQ1[4:0]

hIQ9[4:0]

hIQ6[4:0]

hIQ4[4:0]

hIQ2[4:0]

hIQ0[4:0]

hIQ8[4:0]

FAST CLOCK R

FAST CLOCK L

OR3C80 Datasheet(PDF) 47 Page - Agere Systems