OR3C80 datasheet(70/210 Pages) AGERE

70 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Microprocessor Interface (MPI) (continued)

Status Register

The microprocessor interface status register is a read-only register, providing information to the host processor.

Table 22. Status Register

Configuration Data Register

The MPI configuration data register is a writable register in configuration mode and a readable register in readback

mode. For FPGA configuration, this is where the configuration data bytes are sequentially written by the host pro-

cessor. Similarly, for readback mode, the MPI provides the readback data bytes in this register for the host proces-

sor.

Readback Address Register 1

The MPI readback address register 1 is a writable register used to accept the least significant address byte

(bits [7:0]) of the configuration data location to be read back.

Readback Address Register 2

The MPI readback address register 2 is a writable register used to accept the most significant address byte

(bits [15:8]) of the configuration data location to be read back.

Bit #

Description

Bit 0

Reserved.

Bit 1

Data Ready. Set by the MPI, a 1 on this bit during configuration alerts the host processor that the FPGA

is ready for another byte of configuration data. During byte-wide readback, the MPI sets this bit to a 1 to

tell the host processor that a byte of configuration data is available for reading. This bit is cleared by a

host processor access (read or write) to the configuration data register.

Bit 2

IRQ

Pending. The MPI sets this bit to 1 to indicate to the host processor that the FPGA has a pending

interrupt request. This bit may be used for the host processor to poll for interrupts if the MPI_IRQ pin out-

put of the FPGA has been masked at the host processor. This bit is set to 0 when the status register is

read. Interrupt requests from the FPGA user space must be cleared in FPGA user logic in addition to

reading this bit.

Bits

[4:3]

Bit Stream Error Flags. Bits 3 and 4 are set by the MPI to indicate any error during FPGA configura-

tion. See bit 2 of control register 2 for the capability to alert the host processor of an error via the IRQ

signal during configuration. In the truth table below, bit 3 is the LSB (bit on right). These bits are cleared

to 0 when PRGM goes active:

00 = No error

01 = ID error

10 = Checksum error

11 = Stop-bit/alignment error

Bit 5

Reserved.

Bit 6

INIT.

This bit reflects the binary value of the FPGA INIT pin.

Bit 7

DONE. This bit reflects the binary value of the FPGA DONE pin.

OR3C80 Datasheet(PDF) 70 Page - Agere Systems

OR3C80 Datasheet(HTML) 70 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL