OR3C80 datasheet(37/210 Pages) AGERE

37 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Programmable Input/Output Cells

(continued)

5 V Tolerant I/O

The I/O on the OR3Txxx Series devices allow intercon-

nection to both 3.3 V and 5 V devices (selectable on a

per-pin basis).

The OR3Txxx devices will drive the pin to the 3.3 V lev-

els when the output buffer is enabled. If the other

device being driven by the OR3Txxx device has TTL-

compatible inputs, then the device will not dissipate

much input buffer power. This is because the OR3Txxx

output is being driven to a higher level than the TTL

level required. If the other device has a CMOS-compat-

ible input, the amount of input buffer power will also be

small. Both of these power values are dependent upon

the input buffer characteristics of the other device when

driven at the OR3Txxx output buffer voltage levels.

The OR3Txxx device has internal programmable pull-

ups on the I/O buffers. These pull-up voltages are

always referenced to VDD and are always sufficient to

pull the input buffer of the OR3Txxx device to a high

state. The pin on the OR3Txxx device will be at a level

1.0 V below VDD (minimum of 2.0 V with a minimum

VDD of 3.0 V). This voltage is sufficient to pull the exter-

nal pin up to a 3.3 V CMOS high input level (1.8 V, min)

or a TTL high input level (2.0 V, min) in a 5 V tolerant

system. Therefore, in a 5 V tolerant system using 5 V

CMOS parts, care must be taken to evaluate the use of

these pull-ups to pull the pin of the OR3Txxx device to

a typical 5 V CMOS high input level (2.2 V, min).

PCI Compliant I/O

The I/O on the OR3Txxx Series devices allows compli-

ance with PCI Local Bus (Rev. 2.2) 5 V and 3.3 V sig-

naling environments. The signaling environment used

for each input buffer can be selected on a per-pin basis.

The selection provides the appropriate I/O clamping

diodes for PCI compliance. Choosing an IBT input

buffer will provide PCI compliance in OR3Txxx devices.

OR3Cxx devices have PCI Local Bus compliant I/Os for

5 V signaling.

Table 9. PIO Options

Input

Option

Input Level

TTL, OR3Cxx only

CMOS, OR3Cxx or OR3Txxx

3.3 V PCI Compliant, OR3Txxx

5 V PCI Compliant, OR3Txxx

Input Speed

Fast, Delayed

Float Value

Pull-up, Pull-down, None

Latch, FF, Fast Zero Hold FF,

None (direct input)

Clock Sense

Inverted, Noninverted

Input Selection

Input 1, Input 2, Clock Input

Output

Option

Output Drive

Current

12 mA/6 mA or 6 mA/3 mA

Output Function

Normal, Fast Open Drain

Output Speed

Fast, Slewlim, Sinklim

Output Source

FF Direct-out, General Routing

Output Sense

Active-high, Active-low

3-State Sense

Active-high, Active-low (3-state)

FF Clocking

ExpressCLK

, System Clock

Clock Sense

Inverted, Noninverted

Logic Options

See Table 10.

I/O Controls

Option

Clock Enable

Active-high, Active-low,

Always Enabled

Set/Reset Level

Active-high, Active-low,

No Local Reset

Set/Reset Type

Synchronous, Asynchronous

Set/Reset Priority

CE over LSR, LSR over CE

GSR Control

Enable GSR, Disable GSR

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