OR3C80 datasheet(50/210 Pages) AGERE

50 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Clock Distribution Network

The Series 3 FPGAs provide three types of high-

speed, low-skew clock distributions: system clock, fast

middle clock (fast clock), and ExpressCLK. Because of

the great variety of sources and distribution for clock

signals in the

ORCA Series 3, the clock mechanisms

will be described here from the inside out. The clock

connections to the PFU will be described, followed by

clock distribution to the PLC array, clock sources to the

PLC array, and finally ending with clock sources and

distribution in the PICs. The ExpressCLK inputs are

new, dedicated clock inputs in Series 3 FPGAs. They

are mentioned in several of the clock network descrip-

tions and are described fully later in this section.

PFU Clock Sources

Within a PLC there are five sources for the clock signal

of the latches/FFs in the PFU. Two of the signals are

generated off of the long lines (xL) within the PLC: one

from the set of vertical long lines and one from the set

of horizontal long lines. For each of these signals, any

one of the ten long lines of each set, vertical or horizon-

tal, can generate the clock signal. Two of the five PFU

clock sources come from neighboring PLCs. One clock

is generated from the PLC to the left or right of the cur-

rent PLC, and one is generated from the PLC above or

below the current PLC. The selection decision as to

where these signals come from, above/below and left/

right, is based on the position of the PLC in the array

and has to do with the alternating nature of the source

of the system clock spines (discussed later). The last of

the five clock sources is also generated within the PLC.

The E1 control signal, described in the PLC Routing

Resources section, can drive the PFU clock. The E1

signal can come from any xBID routing resource in the

PLC. The selection and switching of clock signals in a

PLC is performed in the FINS. Figure 31 shows the

PFU clock sources for a set of four adjacent PLCs.

Global Control Signals

The four clock signals in each PLC that are generated

from the long lines (xL) in the current PLC or an adja-

cent PLC can also be used to drive the PFU clock

enable (CE), local set/reset (LSR) and add/subtract/

write enable (ASWE) signals. The clock signals gener-

ated from vertical long lines can drive CE and ASWE,

and the clocks generated from horizontal long lines can

drive LSR. This allows for low-skew global distribution

of two of these three control signals with the clock rout-

ing while still allowing a global clock route to occur.

5-6054(F)

Figure 31. PFU Clock Sources

PFU

PLC

PFU

PLC

PFU

PLC

PFU

PLC

hxL[9:0]

vxL[9:0]

OR3C80 Datasheet(PDF) 50 Page - Agere Systems

OR3C80 Datasheet(HTML) 50 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL