OR3C80 datasheet(94/210 Pages) AGERE

94 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

FPGA Configuration Modes (continued)

Asynchronous Peripheral Mode

Figure 56 shows the connections needed for the asyn-

chronous peripheral mode. In this mode, the FPGA

system interface is similar to that of a microprocessor-

peripheral interface. The microprocessor generates the

control signals to write an 8-bit byte into the FPGA. The

FPGA control inputs include active-low CS0 and active-

high CS1 chip selects and WR and RD inputs. The chip

selects can be cycled or maintained at a static level

during the configuration cycle. Each byte of data is writ-

ten into the FPGA’s D[7:0] input pins. D[7:0] of the

FPGA can be connected to D[7:0] of the microproces-

sor only if a standard prom file format is used. If a .bit or

.rbt file is used from

ORCA Foundry, then the user must

mirror the bytes in the .bit or .rbt file OR leave the .bit or

.rbt file unchanged and connect D[7:0] of the FPGA to

D[0:7] of the microprocessor.

The FPGA provides an RDY/BUSY status output to indi-

cate that another byte can be loaded. A low on RDY/

BUSY

indicates that the double-buffered hold/shift reg-

isters are not ready to receive data, and this pin must

be monitored to go high before another byte of data

can be written. The shortest time RDY/BUSY is low

occurs when a byte is loaded into the hold register and

the shift register is empty, in which case the byte is

immediately transferred to the shift register. The long-

est time for RDY/BUSY to remain low occurs when a

byte is loaded into the holding register and the shift

configuration RAM.

The RDY/BUSY status is also available on the D7 pin by

enabling the chip selects, setting WR high, and apply-

ing RD low, where the RD input provides an output

enable for the D7 pin when RD is low. The D[6:0] pins

are not enabled to drive when RD is low and, therefore,

only act as input pins in asynchronous peripheral

mode. Optionally, the user can ignore the RDY/BUSY

status and simply wait until the maximum time it would

take for the RDY/BUSY line to go high, indicating the

FPGA is ready for more data, before writing the next

data byte.

Figure 56. Asynchronous Peripheral Configuration

Microprocessor Interface

(MPI) Mode

The built-in MPI in Series 3 FPGAs is designed for use

in configuring the FPGA. Figure 57 and Figure 58 show

the glueless interface for FPGA configuration and read-

back from the

PowerPC and i960 processors, respec-

tively. When enabled by the mode pins, the MPI

handles all configuration/readback control and hand-

shaking with the host processor. For single FPGA con-

figuration, the host sets the configuration control

reading that the INIT signal is high in the MPI status

D[7:0] input pins.

If configuring multiple FPGAs through daisy-chain

operation is desired, the MP_DAISY bit must be set in

the configuration control register of the MPI. Because

of the latency involved in a daisy-chain configuration,

the MP_HOLD_BUS bit may be set to zero rather than

one for daisy-chain operation. This allows the MPI to

acknowledge the data transfer before the configuration

information has been serialized and transferred on the

FPGA daisy-chain. The early acknowledgment frees

the host processor to perform other system tasks. Con-

figuring with the MP_HOLD_BUS bit at zero requires

that the host microprocessor poll the RDY/BUSY bit of

the MPI status register and/or use the MPI interrupt

capability to confirm the readiness of the MPI for more

configuration data.

MICRO-

PROCESSOR

D[7:0]

CS1

HDC

ORCA

SERIES

FPGA

LDC

VDD

DONE

CS0

DOUT

CCLK

TO DAISY-

CHAINED

DEVICES

BUS

CONTROLLER

ADDRESS

DECODE LOGIC

RDY/BUSY

INIT

PRGM

OR3C80 Datasheet(PDF) 94 Page - Agere Systems

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