OR3C80 datasheet(62/210 Pages) AGERE

62 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Special Function Blocks (continued)

Boundary-Scan Cells

Figure 40 is a diagram of the boundary-scan cell (BSC)

in the

ORCA series PICs. There are four BSCs in each

PIC: one for each pad, except as noted above. The

BSCs are connected serially to form the BSR. The

BSC controls the functionality of the in, out, and 3-state

signals for each pad.

The BSC allows the I/O to function in either the normal

or test mode. Normal mode is defined as when an out-

put buffer receives input from the PLC array and pro-

vides output at the pad or when an input buffer

provides input from the pad to the PLC array. In the test

mode, the BSC executes a boundary-scan operation,

such as shifting in scan data from an upstream BSC in

the BSR, providing test stimuli to the pad, capturing

test data at the pad, etc.

The primary functions of the BSC are shifting scan data

serially in the BSR and observing input (p_in), output

(p_out), and 3-state (p_ts) signals at the pads. The

BSC consists of two circuits: the bidirectional data cell

is used to access the input and output data, and the

direction control cell is used to access the 3-state

value. Both cells consist of a flip-flop used to shift scan

data which feeds a flip-flop to control the I/O buffer. The

bidirectional data cell is connected serially to the direc-

tion control cell to form a boundary-scan shift register.

The TAPC signals (capture, update, shiftn, treset, and

TCK) and the MODE signal control the operation of the

BSC. The bidirectional data cell is also controlled by

the high out/low in (HOLI) signal generated by the

direction control cell. When HOLI is low, the bidirec-

tional data cell receives input buffer data into the BSC.

When HOLI is high, the BSC is loaded with functional

data from the PLC.

The MODE signal is generated from the decode of the

instruction register. When the MODE signal is high

(EXTEST), the scan data is propagated to the output

buffer. When the MODE signal is low (BYPASS or

SAMPLE), functional data from the FPGA’s internal

logic is propagated to the output buffer.

The boundary-scan description language (BSDL) is

provided for each device in the

ORCA Series of FPGAs

on the

ORCA Foundry CD. The BSDL is generated

from a device profile, pinout, and other boundary-scan

information.

5-2844(F

Figure 40. Boundary-Scan Cell

SCAN IN

p_out

HOLI

BIDIRECTIONAL DATA CELL

I/O BUFFER

DIRECTION CONTROL CELL

MODE

UPDATE/TCK

SCAN OUT

TCK

SHIFTN/CAPTURE

p_ts

p_in

PAD_IN

PAD_TS

PAD_OUT

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