OR3C80 datasheet(25/210 Pages) AGERE

25 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Programmable Logic Cells (continued)

PLC Latches/Flip-Flops

The eight general-purpose latches/FFs in the PFU can

be used in a variety of configurations. In some cases,

the configuration options apply to all eight latches/FFs in

the PFU and

some apply to the latches/FFs on a nibble-

wide basis where the ninth FF is considered indepen-

dently. For other options, each latch/FF is independently

programmable. In addition, the ninth FF can be used for

a variety of functions.

Table 7 summarizes these latch/FF options. The

latches/FFs can be configured as either positive- or

negative-level sensitive latches, or positive or negative

edge-triggered flip-flops (the ninth register can only be

FF). All latches/FFs in a given PFU share the same

clock, and the clock to these latches/FFs can be

inverted. The input into each latch/FF is from either the

corresponding LUT output (F[7:0]) or the direct data

input (DIN[7:0]). The latch/FF input can also be tied to

logic 1 or to logic 0, which is the default.

* Not available for FF[8].

The eight latches/FFs in a PFU share the clock (CLK)

and options for clock enable (CE), local set/reset (LSR),

and front-end data select (SEL) inputs. When CE is dis-

abled, each latch/FF retains its previous value when

clocked. The clock enable, LSR, and SEL inputs can be

inverted to be active-low.

The set/reset operation of the latch/FF is controlled by

two parameters: reset mode and set/reset value. When

the global set/reset (

GSRN) and local set/reset (LSR)

signals are not asserted, the latch/FF operates normally.

The reset mode is used to select a synchronous or

asynchronous LSR operation. If synchronous, LSR has

the option to be enabled only if clock enable (CE or

ASWE) is active or for LSR to have priority over the

clock enable input, thereby setting/resetting the FF inde-

pendent of the state of the clock enable. The clock

enable is supported on FFs, not latches. It is imple-

mented by using a 2-input multiplexer on the FF input,

with one input being the previous state of the FF and the

other input being the new data applied to the FF. The

select of this 2-input multiplexer is clock enable (CE or

ASWE), which selects either the new data or the previ-

ous state. When the clock enable is inactive, the FF out-

put does not change when the clock edge arrives.

Table 7. Configuration RAM Controlled Latch/

Flip-Flop Operation

Function

Options

Common to All Latches/FFs in PFU

LSR Operation

Asynchronous or synchronous

Clock Polarity

Noninverted or inverted

Front-end Select*

Direct (DIN[7:0])or from LUT (F[7:0])

LSR Priority

Either LSR or CE has priority

Latch/FF Mode

Latch or flip-flop

Enable GSRN

GSRN enabled or has no effect on

PFU latches/FFs

Set Individually in Each Latch/FF in PFU

Set/Reset Mode

Set or reset

By Group (Latch/FF[3:0], Latch/FF[7:4], and FF[8])

Clock Enable

CE or ASWE or none

LSR Control

LSR or none

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