OR3C80 datasheet(68/210 Pages) AGERE

68 / 210 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Microprocessor Interface (MPI) (continued)

MPI Setup and Control

The MPI has a series of addressable registers that provide MPI control and status, configuration and readback data

transfer, FPGA device identification, and a dedicated user scratchpad register. All registers are 8 bits wide. The

address map for these registers and the user-logic address space are shown in Table 19, followed by descriptions

of the register and bit functions. Note that for all registers, the most significant bit is bit 7, and the least significant bit

is bit 0.

Table 19. MPI Setup and Control Registers

Control Register 1

The MPI control register 1 is a read/write register. The host processor writes a control byte to configure the MPI. It

is readable by the host processor to verify the status of control bits previously written.

Table 20. MPI Setup and Control Registers Descriptions

Address

(Hex)

Control Register 1.

Control Register 2.

Scratchpad Register.

Status Register.

Configuration/Readback Data Register.

Readback Address Register 1 (bits [7:0]).

Readback Address Register 2 (bits [15:8]).

Device ID Register 1 (bits [7:0]).

Device ID Register 2 (bits [15:8]).

Device ID Register 3 (bits [23:16]).

Device ID Register 4 (bits [31:24]).

0B—0F

Reserved.

10—1F

User-definable Address Space.

Bit #

Description

Bit 0

GSR Input. Setting this bit to a 1 invokes a global set/reset on the FPGA. The host processor must

return this bit to a 0 to remove the GSR signal. GSR does not affect the registers at MPI addresses 0

through F hexadecimal or any configuration registers. Default state = 0.

Bit 1

Reserved.

Bit 2

Reserved.

Bit 3

Reserved.

Bit 4

Reserved.

Bit 5

RD_CFG

Input. Changing this bit to a 0 after configuration will initiate readback. The host processor

must return this bit to a 1 to remove the RD_CFG signal. Since this bit works exactly like the RD_CFG

input pin, please see the FPGA pin descriptions for more information on this signal. Default state = 1.

Bit 6

Reserved.

Bit 7

PRGM

Input. Setting this bit to a 0 causes the FPGA to begin configuration and resets the boundary-

scan circuitry. The host processor must return this bit to a 1 to remove the PRGM signal. Since this bit

works exactly like the PRGM input pin (except that it does not reset the MPI), please see the FPGA pin

descriptions for more information on this signal. Default state = 1.

OR3C80 Datasheet(PDF) 68 Page - Agere Systems

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